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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338P-B05983-GMR

Name: SI5338P-B05983-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338P-B05983-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338P-B05983-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338P-B05983-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338P-B05983-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338P-B05983-GMR datasheet, SI5338P-B05983-GMR pinout, SI5338P-B05983-GMR application, or SI5338P-B05983-GMR equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ fractional synthesis resolution (1 ppb), spread-spectrum control (0.5–5.0% deviation), and loss-of-lock/loss-of-signal alarm support.

Technical Context

The SI5338P-B05983-GMR implements a two-stage PLL architecture: a high-stability reference stage (input frequency range 5–710 MHz) followed by four independent MultiSynth™ synthesis blocks, each supporting integer or fractional-N division with programmable R, M, and P dividers. Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with per-output VDDO selection.

It features pin-controlled or I²C-configurable frequency increment/decrement (1 ppm steps), phase adjustment (<20 ps resolution), and spread-spectrum modulation (33–63 kHz rate, 0.5–5.0% spread). External feedback mode enables zero-delay operation, and status monitoring includes INTR pin assertion for loss-of-lock and loss-of-signal events.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS).
Output Count & Type	Four differential outputs (CLK0A/B–CLK3A/B); supports up to eight single-ended clocks via configuration.
Frequency Range	0.16–710 MHz per output; supports >350 MHz on two outputs simultaneously (Fvco/4 and Fvco/6).
Input Flexibility	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz).
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; output buffers: independently configurable 1.5/1.8/2.5/3.3 V.
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, halogen-free, GMR suffix indicates green packaging.
Operating Temp	–40 °C to +85 °C ambient; qualified for industrial and telecom line card environments.

Pinout & Package

SI5338P-B05983-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed across Si5338 family variants and validated per Skyworks Rev. 1.6 datasheet Figure 1 (Top View).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept AC-coupled LVDS/LVPECL/CML references (5–710 MHz); require external 100 Ω termination.
IN3, IN4	Single-ended inputs	Support CMOS/SSTL/HSTL (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD; internal 20 kΩ pull-up/down options.
CLK0A–CLK3B	Differential output pairs	Four independent output drivers; each configurable as LVPECL/LVDS/HCSL/CML with per-driver VDDO.
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V supplies per output bank; decoupling required per datasheet layout guidelines.
VDD	Core supply	Single 1.8/2.5/3.3 V core rail; PSRR optimized for low-noise clock generation.
SCL, SDA	I²C interface	SMBus-compatible 100/400 kHz interface; supports write-protection and register lock after programming.
INTR	Interrupt output	Open-drain status pin asserting on loss-of-lock, loss-of-signal, or NVM error; requires external pull-up.
OEB, PINC, FINC	Control inputs	Hardware pins for output enable, phase/frequency increment; enable glitchless real-time tuning without I²C traffic.

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling true zero-ppm accuracy on all outputs with 1 ppb resolution.
PCIe Gen 4 compliance	Validated RMS jitter ≤0.45 ps (10 kHz–50 MHz) in common clock mode; meets SRNS requirements for Gen 3.
Per-output voltage control	Each of four output banks powered by dedicated VDDOx rail (1.5/1.8/2.5/3.3 V), eliminating level-shifter ICs in mixed-voltage systems.
Hardware frequency tuning	PINC/FINC pins allow sub-microsecond, glitchless frequency adjustments in 1 ppm steps-critical for dynamic link training.
Programmable spread spectrum	Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, reducing EMI peaks without affecting timing margin.
Loss-of-signal detection	Fast LOS response (2.6–5 µs detect, 0.01–1 µs release) enables rapid failover in redundant clock architectures.

Applications

Ethernet Switch Timing	PCIe Gen 4 Server Interconnect
Use Scenario: 10 GbE/25 GbE switch fabric requiring synchronized 156.25 MHz and 312.5 MHz clocks across multiple PHYs and MACs. IC Role / Device Role / Timing Role: Quad clock generator providing four low-jitter, independently configured clocks-one per SerDes lane group-with matched skew and SSC for EMI reduction. Use Value: Eliminates four discrete oscillators; achieves <100 ps output-to-output skew and 0.7 ps RMS jitter, meeting IEEE 802.3bj jitter budgets.	Use Scenario: CPU-to-GPU or CPU-to-ASIC interconnect in AI accelerators using PCIe Gen 4 x16 links with strict common clock jitter limits. IC Role / Device Role / Timing Role: Primary system clock source delivering 100 MHz common reference to root complex and endpoints with Gen 4-compliant jitter (≤0.45 ps RMS). Use Value: Passes Intel Clock Jitter Tool validation; supports hardware frequency tuning during link training without firmware intervention.
Broadcast Video Synchronization	FPGA-Based Protocol Converter
Use Scenario: SMPTE ST 2082 (12G-SDI) video router requiring precise 74.25 MHz and 148.5 MHz clocks with sub-ns phase alignment across 32 channels. IC Role / Device Role / Timing Role: Master timing engine generating four synchronized outputs with programmable initial phase offset (±45 ns, <20 ps step). Use Value: Enables deterministic skew compensation across long PCB traces; supports frame-accurate genlock via I²C-triggered phase adjust.	Use Scenario: FPGA-based 10GBase-R to CPRI converter needing 156.25 MHz (Ethernet), 307.2 MHz (CPRI), and 122.88 MHz (eCPRI) clocks from a single reference. IC Role / Device Role / Timing Role: Any-frequency synthesizer translating a 25 MHz crystal into three non-integer-related frequencies with zero ppm error. Use Value: Replaces three separate PLLs; achieves 0.16–710 MHz coverage per output with identical jitter performance across all formats.

Ethernet Switch Timing

PCIe Gen 4 Server Interconnect

Use Scenario: 10 GbE/25 GbE switch fabric requiring synchronized 156.25 MHz and 312.5 MHz clocks across multiple PHYs and MACs.

IC Role / Device Role / Timing Role: Quad clock generator providing four low-jitter, independently configured clocks-one per SerDes lane group-with matched skew and SSC for EMI reduction.

Use Value: Eliminates four discrete oscillators; achieves <100 ps output-to-output skew and 0.7 ps RMS jitter, meeting IEEE 802.3bj jitter budgets.

Use Scenario: CPU-to-GPU or CPU-to-ASIC interconnect in AI accelerators using PCIe Gen 4 x16 links with strict common clock jitter limits.

IC Role / Device Role / Timing Role: Primary system clock source delivering 100 MHz common reference to root complex and endpoints with Gen 4-compliant jitter (≤0.45 ps RMS).

Use Value: Passes Intel Clock Jitter Tool validation; supports hardware frequency tuning during link training without firmware intervention.

Broadcast Video Synchronization

FPGA-Based Protocol Converter

Use Scenario: SMPTE ST 2082 (12G-SDI) video router requiring precise 74.25 MHz and 148.5 MHz clocks with sub-ns phase alignment across 32 channels.

IC Role / Device Role / Timing Role: Master timing engine generating four synchronized outputs with programmable initial phase offset (±45 ns, <20 ps step).

Use Value: Enables deterministic skew compensation across long PCB traces; supports frame-accurate genlock via I²C-triggered phase adjust.

Use Scenario: FPGA-based 10GBase-R to CPRI converter needing 156.25 MHz (Ethernet), 307.2 MHz (CPRI), and 122.88 MHz (eCPRI) clocks from a single reference.

IC Role / Device Role / Timing Role: Any-frequency synthesizer translating a 25 MHz crystal into three non-integer-related frequencies with zero ppm error.

Use Value: Replaces three separate PLLs; achieves 0.16–710 MHz coverage per output with identical jitter performance across all formats.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B05983-GM	Same silicon, different factory-programmed NVM image; B05983-GM lacks preloaded configuration and requires full I²C initialization.	No preprogrammed startup behavior; requires external microcontroller or EEPROM for boot-time clock delivery.	Select B05983-GM only if custom configuration is mandatory and boot-time clocking is handled externally.
LMK04832RHAR	Two PLLs (not four independent synthesizers); higher power (120 mA vs. 45 mA typ); larger 48-QFN package.	Targeted at JESD204B/JESD204C converter timing; lacks per-output VDDO and hardware PINC/FINC controls.	Choose LMK04832RHAR only when dual-loop cascaded jitter cleaning is required over independent multi-frequency synthesis.

Compared with Si5338A-B05983-GM and LMK04832RHAR, SI5338P-B05983-GMR delivers factory-programmed, plug-and-play operation with lowest power and smallest footprint-ideal for PCIe Gen 4 and multi-gigabit Ethernet where startup reliability and board space are critical.

Availability

SI5338P-B05983-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server interconnects, 10/25 GbE switch timing, broadcast video synchronization, and FPGA-based protocol conversion requiring stable component supply and guaranteed long-term availability.

Supply support for SI5338P-B05983-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with broad portfolio certification for automotive, industrial, and communications markets.

The Si5338 product line was designed specifically for high-performance, multi-frequency clock generation in datacenter, telecom, and broadcast equipment-emphasizing ultra-low jitter, flexible I/O, and field-programmable versatility without sacrificing power or size.

FAQ

What is the factory-programmed configuration of the SI5338P-B05983-GMR?

The SI5338P-B05983-GMR ships with a preloaded NVM image configured for PCIe Gen 4 common clock operation: 100 MHz LVDS outputs on CLK0A/B and CLK1A/B, 100 MHz HCSL on CLK2A/B, and 100 MHz LVPECL on CLK3A/B-all derived from a 25 MHz crystal input. This eliminates boot-time I²C programming and ensures immediate clock validity within 2 ms of power-up.

Does the SI5338P-B05983-GMR support spread-spectrum clocking (SSC) on all four outputs simultaneously?

Yes, the SI5338P-B05983-GMR supports independent spread-spectrum modulation on any output: frequency deviation (0.5–5.0%), modulation rate (33–63 kHz), and direction (down-spread or center-spread) are fully programmable per output via I²C registers. Hardware SSC control is not available; configuration requires register writes.

Can the SI5338P-B05983-GMR generate four different frequencies above 350 MHz?

No. The SI5338P-B05983-GMR can output two unique frequencies above 350 MHz simultaneously-specifically Fvco/4 and Fvco/6-due to VCO architecture constraints. Other outputs above 350 MHz must duplicate one of those two frequencies. For example, CLK0A/B and CLK1A/B may run at 473.33 MHz and 550 MHz, while CLK2A/B and CLK3A/B must match one of those values.

What is the minimum input frequency supported in PLL bypass (clock buffer) mode for the SI5338P-B05983-GMR?

In PLL bypass mode, the SI5338P-B05983-GMR supports input frequencies as low as 1 MHz on single-ended inputs (IN3/IN4) and 5 MHz on differential inputs (IN1/IN2, IN5/IN6). However, loss-of-signal detection is disabled below 5 MHz, and additive phase jitter increases to 0.165 ps RMS (12 kHz–20 MHz) at 622.08 MHz input.

How does the SI5338P-B05983-GMR handle power supply sequencing between VDD and VDDOx rails?

The SI5338P-B05983-GMR has no strict power sequencing requirement: VDD (core) and VDDOx (output buffers) may be powered in any order. All outputs remain in high-impedance state until VDD stabilizes and internal POR completes (~15 ms), preventing bus contention. VDDOx sequencing is irrelevant since each output bank is isolated and enabled only after its respective VDDOx reaches valid threshold.

SI5338P-B05983-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338P-B05983-GMR FAQ

1.How can I place an order for SI5338P-B05983-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338P-B05983-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338P-B05983-GMR reliable?

The price and inventory of SI5338P-B05983-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338P-B05983-GMR is usually 5 days.

3.What payment methods are accepted for SI5338P-B05983-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338P-B05983-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338P-B05983-GMR?

SI5338P-B05983-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338P-B05983-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338P-B05983-GMR?

For technical support, including SI5338P-B05983-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338P-B05983-GMR requirements.

6.How does Aetrix verify that SI5338P-B05983-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338P-B05983-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338P-B05983-GMR meets industry standards.

7.What is the process for return or replacement of SI5338P-B05983-GMR?

All SI5338P-B05983-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338P-B05983-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338P-B05983-GMR part is unused and in its original packaging.

Return procedure for SI5338P-B05983-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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