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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338P-B06004-GMR

Name: SI5338P-B06004-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338P-B06004-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338P-B06004-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338P-B06004-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338P-B06004-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent differential or single-ended clocks (0.16–710 MHz), 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing.

For engineers reviewing the SI5338P-B06004-GMR datasheet, SI5338P-B06004-GMR pinout, SI5338P-B06004-GMR application, or SI5338P-B06004-GMR equivalent, key selection criteria include output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL), per-output voltage control (1.5–3.3 V), independent phase/frequency adjustment (±45 ns / 1 ppm steps), spread-spectrum capability (0.5–5.0% at 33–63 kHz), and PCIe Gen 4 SRNS-compliant jitter performance.

Technical Context

The SI5338P-B06004-GMR integrates a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesizers, each feeding a configurable output driver. This enables true any-frequency synthesis with zero-ppm accuracy on all outputs.

It supports multiple input configurations - differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or 8–30 MHz crystal - and offers full output independence: format, voltage, enable, phase offset, and spread-spectrum parameters are set per channel via I²C or hardware pins.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 differential outputs (CLK0A/B to CLK3A/B), configurable as LVPECL/LVDS/HCSL/CML/SSTL/HSTL or 8 single-ended CMOS outputs
Frequency range	0.16–710 MHz per output; supports ≥2 frequencies >350 MHz simultaneously (Fvco/4 and Fvco/6)
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock and SRNS requirements
Input reference	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz)
Supply voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating temp	–40 to +85 °C ambient; qualified for industrial and telecom line card applications

Pinout & Package

SI5338P-B06004-GMR is housed in a 24-lead, 4 × 4 mm QFN package with an exposed thermal pad. Pin assignments follow the standard Si5338 top-view layout: IN1/IN2 (differential ref 1), IN3/IN4 (single-ended ref), IN5/IN6 (differential ref 2), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA/INTR (I²C interface and interrupt), and GND/RSVD_GND.

Pin/Terminal	Circuit Role	Design Meaning
CLK0A / CLK0B	Differential output pair 0	Configurable as LVPECL/LVDS/HCSL/CML; supports 0.16–710 MHz; independent voltage (VDDO0) and enable
CLK1A / CLK1B	Differential output pair 1	Same format/voltage/frequency flexibility as CLK0; fully independent timing path
CLK2A / CLK2B	Differential output pair 2	Supports HCSL up to 250 MHz; enables PCIe Gen 3/4 clocking with <0.32 ps RMS jitter
CLK3A / CLK3B	Differential output pair 3	Independent phase adjustment (<20 ps step), spread-spectrum modulation, and loss-of-signal monitoring
IN1 / IN2	Differential reference input 1	Accepts 5–710 MHz AC-coupled signal; internal 100 Ω termination; optimized for low-jitter injection
IN3 / IN4	Single-ended reference inputs	CMOS-compatible (5–200 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD; slew rate >1 V/ns recommended
VDDO0–VDDO3	Output buffer supplies	Each powers one output pair; allows mixed-voltage system clocking (e.g., 1.8 V FPGA + 3.3 V PHY)
SCL / SDA	I²C serial interface	SMBus-compatible; supports ClockBuilder Pro programming; 400 kHz standard mode
INTR	Interrupt output	Open-drain status flag for loss-of-lock (LOL) or loss-of-signal (LOS); active-low assertion

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling zero-ppm any-frequency generation per output without external components
Per-output voltage control	Each of four output banks powered by dedicated VDDOx pins (1.5/1.8/2.5/3.3 V), eliminating level-shifting ICs in mixed-voltage systems
Glitchless frequency tuning	Hardware pin-controlled frequency increment/decrement in 1 ppm steps with <667 ns update time above 18 MHz
Programmable phase offset	±45 ns range per output with <20 ps resolution, enabling precise skew alignment across SerDes lanes or memory interfaces
Spread-spectrum clocking	Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate, reducing EMI in dense PCB layouts

Applications

PCIe Gen 4 Switch Timing	Ethernet 10GbE Line Card
Use Scenario: High-density switch ASIC requiring four synchronized, low-jitter clocks (100 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for PCIe Gen 4 root complex, upstream/downstream ports, and management controller. IC Role / Device Role / Timing Role: Quad clock generator providing independent, SRNS-compliant reference clocks with <0.32 ps RMS jitter per PCIe Gen 4 spec. Use Value: Eliminates four discrete oscillators and associated layout complexity while meeting strict PCIe Gen 4 jitter masks without external filtering.	Use Scenario: 10GbE line card with dual MACs, PHYs, and packet processor needing matched 156.25 MHz and 312.5 MHz clocks with sub-100 ps inter-output skew. IC Role / Device Role / Timing Role: Low-jitter clock source generating differential LVDS clocks with programmable phase alignment between data paths. Use Value: Achieves <100 ps output-to-output skew and 0.7 ps RMS jitter, ensuring clean sampling margins for 10GBase-R and SFI interfaces.
Broadcast Video Sync Generator	FPGA-Based Telecom Processing
Use Scenario: Broadcast video equipment requiring SMPTE 2081/2082 compliant 27 MHz, 74.25 MHz, and 148.5 MHz clocks with tight phase coherence across HD/4K/8K signal chains. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer delivering three precisely phase-aligned outputs from a single 27 MHz crystal reference. Use Value: Enables zero-ppm frequency accuracy and <20 ps phase step resolution, critical for genlock stability and frame-accurate video switching.	Use Scenario: Telecom baseband unit with FPGA, ADC/DAC, and CPRI/eCPRI interfaces demanding 30.72 MHz, 122.88 MHz, and 245.76 MHz clocks with ultra-low additive jitter. IC Role / Device Role / Timing Role: Low-noise clock generator operating in PLL bypass mode for <0.165 ps RMS additive jitter on high-frequency inputs. Use Value: Provides sub-0.2 ps RMS additive jitter in buffer mode, preserving signal integrity for wideband RF sampling and digital predistortion.

PCIe Gen 4 Switch Timing

Ethernet 10GbE Line Card

Use Scenario: High-density switch ASIC requiring four synchronized, low-jitter clocks (100 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for PCIe Gen 4 root complex, upstream/downstream ports, and management controller.

IC Role / Device Role / Timing Role: Quad clock generator providing independent, SRNS-compliant reference clocks with <0.32 ps RMS jitter per PCIe Gen 4 spec.

Use Value: Eliminates four discrete oscillators and associated layout complexity while meeting strict PCIe Gen 4 jitter masks without external filtering.

Use Scenario: 10GbE line card with dual MACs, PHYs, and packet processor needing matched 156.25 MHz and 312.5 MHz clocks with sub-100 ps inter-output skew.

IC Role / Device Role / Timing Role: Low-jitter clock source generating differential LVDS clocks with programmable phase alignment between data paths.

Use Value: Achieves <100 ps output-to-output skew and 0.7 ps RMS jitter, ensuring clean sampling margins for 10GBase-R and SFI interfaces.

Broadcast Video Sync Generator

FPGA-Based Telecom Processing

Use Scenario: Broadcast video equipment requiring SMPTE 2081/2082 compliant 27 MHz, 74.25 MHz, and 148.5 MHz clocks with tight phase coherence across HD/4K/8K signal chains.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer delivering three precisely phase-aligned outputs from a single 27 MHz crystal reference.

Use Value: Enables zero-ppm frequency accuracy and <20 ps phase step resolution, critical for genlock stability and frame-accurate video switching.

Use Scenario: Telecom baseband unit with FPGA, ADC/DAC, and CPRI/eCPRI interfaces demanding 30.72 MHz, 122.88 MHz, and 245.76 MHz clocks with ultra-low additive jitter.

IC Role / Device Role / Timing Role: Low-noise clock generator operating in PLL bypass mode for <0.165 ps RMS additive jitter on high-frequency inputs.

Use Value: Provides sub-0.2 ps RMS additive jitter in buffer mode, preserving signal integrity for wideband RF sampling and digital predistortion.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B06004-GM	Same silicon die and pinout; factory-programmed OTP configuration differs - B06004-GM uses default register map, while SI5338P-B06004-GMR includes pre-loaded custom configuration for PCIe Gen 4 common clock mode.	Requires no initial I²C programming for PCIe use case; reduces bring-up time vs. blank Si5338A variant.	Select SI5338P-B06004-GMR when PCIe Gen 4 common clock timing is primary requirement and field reprogramming is not needed.
LMK04832ISQE/NOPB	Two-stage jitter cleaner (not pure synthesizer); higher power (120 mA core), larger 7 × 7 mm package; supports JESD204B deterministic latency but lacks per-output voltage control.	Better suited for RF sampling where jitter cleaning > synthesis flexibility is required; not drop-in compatible due to different pinout and power architecture.	Choose LMK04832ISQE/NOPB only when additive jitter cleaning from noisy sources is critical and board space permits larger footprint.

Compared with Si5338A-B06004-GM and LMK04832ISQE/NOPB, SI5338P-B06004-GMR delivers optimal balance of PCIe Gen 4 compliance, compact 4 × 4 mm packaging, per-output voltage control, and factory-tuned configuration - making it ideal for space-constrained, multi-standard serial interface timing where rapid deployment and low component count are priorities.

Availability

SI5338P-B06004-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch design, 10GbE line cards, and broadcast video sync generators requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338P-B06004-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed specifically for high-performance, multi-protocol serial interface timing - addressing PCIe, Ethernet, Fibre Channel, and broadcast video applications with flexible, low-jitter clock synthesis in minimal footprint.

FAQ

What is the maximum output frequency supported by SI5338P-B06004-GMR in LVPECL format?

The SI5338P-B06004-GMR supports LVPECL outputs up to 710 MHz, as confirmed in Table 6 of the datasheet under "Output Clocks (Differential)" for LVPECL/LVDS/CML. This applies when using integer-mode MultiSynth synthesis and proper termination (100 Ω differential load). The device can simultaneously deliver two frequencies above 350 MHz - specifically Fvco/4 and Fvco/6 - making it suitable for high-speed SerDes applications requiring multiple GHz-range references.

Does SI5338P-B06004-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338P-B06004-GMR is explicitly compliant with PCIe Gen 4 SRNS requirements, achieving 0.11–0.32 ps RMS jitter (typ/max) under specified test conditions (PLL BW 2–5 MHz, CDR = 10 MHz), as documented in Table 12. Its independent output configuration, low intrinsic jitter (0.7 ps RMS), and programmable loop bandwidth allow precise tuning to meet SRNS mask limits without external components.

Can SI5338P-B06004-GMR generate four different output voltages simultaneously?

Yes, SI5338P-B06004-GMR supports independent output supply voltages per bank: VDDO0 powers CLK0A/B, VDDO1 powers CLK1A/B, VDDO2 powers CLK2A/B, and VDDO3 powers CLK3A/B. Each accepts 1.5 V, 1.8 V, 2.5 V, or 3.3 V, enabling simultaneous generation of LVDS (2.5 V), HCSL (1.8 V), CMOS (3.3 V), and SSTL (1.5 V) signals - critical for interfacing heterogeneous logic families on a single board.

What is the purpose of the INTR pin on SI5338P-B06004-GMR?

The INTR pin on SI5338P-B06004-GMR is an open-drain interrupt output that asserts low during loss-of-lock (LOL) or loss-of-signal (LOS) events. It provides real-time fault detection for system monitoring and fail-safe response - for example, triggering a processor reset or switching to backup clock source. Its rise/fall time is <10 ns (with 1 kΩ pull-up), and it operates across the full –40 to +85 °C temperature range.

How is SI5338P-B06004-GMR programmed, and is external nonvolatile memory required?

SI5338P-B06004-GMR is programmed via its I²C/SMBus-compatible interface using Skyworks' ClockBuilder Pro software. It contains on-chip one-time-programmable (OTP) NVM that stores the configuration; no external memory is required. The "P" suffix in the part number indicates factory-programmed OTP content - specifically tuned for PCIe Gen 4 common clock operation - enabling immediate functionality after power-up without host processor intervention.

SI5338P-B06004-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338P-B06004-GMR FAQ

1.How can I place an order for SI5338P-B06004-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338P-B06004-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338P-B06004-GMR reliable?

The price and inventory of SI5338P-B06004-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338P-B06004-GMR is usually 5 days.

3.What payment methods are accepted for SI5338P-B06004-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338P-B06004-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338P-B06004-GMR?

SI5338P-B06004-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338P-B06004-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338P-B06004-GMR?

For technical support, including SI5338P-B06004-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338P-B06004-GMR requirements.

6.How does Aetrix verify that SI5338P-B06004-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338P-B06004-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338P-B06004-GMR meets industry standards.

7.What is the process for return or replacement of SI5338P-B06004-GMR?

All SI5338P-B06004-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338P-B06004-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338P-B06004-GMR part is unused and in its original packaging.

Return procedure for SI5338P-B06004-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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