Skyworks Solutions Inc. SI5338P-B-GMR

Overview

SI5338P-B-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis with 0 ppm precision per output, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL outputs up to 710 MHz. It replaces multiple crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338P-B-GMR datasheet, SI5338P-B-GMR pinout, SI5338P-B-GMR application, or SI5338P-B-GMR equivalent, key selection criteria include differential output jitter performance (0.7 ps RMS), independent per-output voltage control (1.5/1.8/2.5/3.3 V), flexible input reference support (8–30 MHz crystal or 5–710 MHz differential), and PCIe Gen 4 common-clock compliance.

Technical Context

The SI5338P-B-GMR integrates a high-stability PLL-based synthesis stage followed by four independent MultiSynth™ fractional-N dividers, enabling any-frequency generation on each of four differential output drivers. Its architecture supports both integer and fractional synthesis modes, with programmable loop bandwidth (1.6 MHz typical) and external feedback for zero-delay operation.

Each output driver features independent format selection (LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL), independent supply voltage (VDDOx = 1.4–3.63 V), and fine-grained phase adjustment (<20 ps step resolution). Input flexibility includes six dedicated clock inputs: two differential pairs (IN1/IN2, IN5/IN6), two single-ended (IN3/IN4), and two additional inputs (IN6 referenced as spare in pinout).

Key Specifications

Pinout & Package

SI5338P-B-GMR uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Compared with Si5332A-D-GM and ICS8430I-01T, the SI5338P-B-GMR uniquely balances full programmability, PCIe Gen 4 compliance, compact 24-QFN footprint, and industrial temperature range-making it optimal for cost-sensitive, space-constrained embedded systems requiring four precisely controlled clocks.

Availability

SI5338P-B-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server boards, 100G Ethernet switches, and broadcast video synchronizers requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338P-B-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for infrastructure and mobility markets.

The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and broadcast video-enabling system architects to consolidate timing functions into a single programmable device.

FAQ

What is the maximum output frequency supported by the SI5338P-B-GMR?

The SI5338P-B-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be simultaneously generated (Fvco/4 and Fvco/6), as confirmed in Table 6 of the datasheet. All outputs maintain 0.7 ps RMS jitter at rated frequencies.

Does the SI5338P-B-GMR support PCIe Gen 4 common-clock architecture?

Yes, the SI5338P-B-GMR is explicitly compliant with PCIe Gen 4 common-clock specifications, delivering ≤0.45 ps RMS jitter (10 kHz–50 MHz) under defined test conditions. This compliance is verified per PCI-Express Base Specification 4.0 rev. 0.5 and measured using the Skyworks PCIe Clock Jitter Tool, confirming suitability for root complex and endpoint timing in Gen 4 systems.

How many independent supply voltages does the SI5338P-B-GMR support for its output drivers?

The SI5338P-B-GMR supports four independent output buffer supply voltages (VDDO0–VDDO3), each configurable from 1.4 V to 3.63 V. This allows direct interfacing with mixed-voltage components-such as 1.8 V SerDes, 2.5 V PHYs, and 3.3 V microcontrollers-without external level shifters, as specified in Table 1 and Table 3 of the datasheet.

Can the SI5338P-B-GMR generate different output formats simultaneously?

Yes, the SI5338P-B-GMR supports simultaneous mixed-format outputs: for example, LVDS on CLK0, HCSL on CLK1, CMOS on CLK2, and SSTL on CLK3-all independently configured. Each output driver accepts format selection via I²C registers, and voltage per driver is set via its dedicated VDDO pin, enabling heterogeneous system timing in a single device.

What is the function of the INTR pin on the SI5338P-B-GMR?

The INTR pin on the SI5338P-B-GMR is an open-drain interrupt output that asserts low to indicate loss-of-lock (LOL) or loss-of-signal (LOS) events detected on any input clock. It is electrically compatible with 1.8/2.5/3.3 V logic systems and supports pull-up resistor configurations per Table 7, enabling real-time fault monitoring without polling the I²C interface.