Skyworks Solutions Inc. SI5338Q-B04069-GM
- Part No.:
- SI5338Q-B04069-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338Q-B04069-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338Q-B04069-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.
For engineers reviewing the SI5338Q-B04069-GM datasheet, SI5338Q-B04069-GM pinout, SI5338Q-B04069-GM application, or SI5338Q-B04069-GM equivalent, this page delivers verified specifications, validated pin functions, confirmed PCIe/10GbE/Ethernet switch use cases, and two technically documented alternative parts for frequency-agile clocking designs requiring low-jitter synthesis and flexible output formatting.
Technical Context
The SI5338Q-B04069-GM implements a dual-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesizers per output channel. Each synthesizer supports integer or fractional mode operation, enabling any-frequency generation from 0.16 MHz to 710 MHz with true zero-ppm accuracy on all outputs.
It features fully independent output drivers supporting LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, programmable per-output supply voltages (1.5/1.8/2.5/3.3 V), and hardware- or I²C-controlled phase/frequency increment/decrement with <20 ps step resolution and glitchless updates. The device also integrates loss-of-lock and loss-of-signal alarms, spread-spectrum control, and external feedback for zero-delay mode.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS & Gen 4 common clock jitter requirements. |
| Output Frequency Range | 0.16–710 MHz per channel; supports up to two >350 MHz outputs simultaneously (Fvco/4 and Fvco/6). |
| Input Reference Support | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz). |
| Output Format Flexibility | Four differential outputs (LVPECL/LVDS/HCSL/CML) or eight single-ended (CMOS/SSTL/HSTL), or mixed configuration. |
| Supply Voltages | Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.4–3.63 V per driver. |
| Temperature Range | –40 to +85 °C ambient; qualified for industrial and telecom line card deployment. |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, exposed thermal pad. |
Pinout & Package
The SI5338Q-B04069-GM is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Pin numbering follows standard top-view orientation with Pin 1 at top-left corner adjacent to the marking dot.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2 | Differential Input 1 | Accepts AC-coupled differential clock (5–710 MHz); requires external 100 Ω termination. |
| IN3, IN4 | Single-Ended Input | DC-coupled CMOS/SSTL/HSTL input (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD. |
| CLK0A, CLK0B – CLK3A, CLK3B | Differential Output Pairs | Four independent differential output channels; each configurable for LVPECL/LVDS/HCSL/CML format and voltage. |
| VDDO0–VDDO3 | Output Buffer Supplies | Independent 1.4–3.63 V supplies per output bank; enables mixed-voltage signaling on same device. |
| VDD | Core Supply | Single 1.8/2.5/3.3 V core supply; PSRR optimized for noise-sensitive timing applications. |
| SCL, SDA | I²C Interface | SMBus-compatible 1.8/2.5/3.3 V tolerant serial interface; supports standard/fast-mode speeds. |
| INTR | Interrupt Output | Open-drain status indicator for loss-of-lock, loss-of-signal, or programming completion events. |
| GND, RSVD_GND | Ground Terminals | Multiple GND pins including dedicated reserved ground; critical for low-jitter signal integrity and thermal dissipation. |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ Synthesis | Four independent fractional-N synthesizers enable simultaneous any-frequency generation with 1 ppb resolution and zero ppm error. |
| PCIe Gen 4 Compliance | Meets PCIe Gen 4 common clock RMS jitter spec (≤0.45 ps RMS) with PLL BW 2–5 MHz and CDR = 10 MHz. |
| Glitchless Frequency Tuning | Hardware pin-controlled frequency increment/decrement in 1 ppm steps without output interruption. |
| Programmable Phase Offset | ±45 ns initial phase adjustment per output with <20 ps step resolution for skew compensation. |
| Spread Spectrum Control | Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, 5–350 MHz frequency range. |
| Low-Power Operation | 45 mA typical core current at 100 MHz on all outputs; 12 mA in buffer-only mode. |
Applications
| Ethernet Switch/Routing Timing | PCIe Gen 1–4 Clocking |
|---|---|
Use Scenario: High-density 1/10 GbE switch fabric requiring synchronized clocks across multiple PHYs, MACs, and packet processors. IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 125 MHz, 156.25 MHz, and 312.5 MHz clocks with matched phase alignment and sub-ps jitter. Use Value: Eliminates four discrete oscillators; reduces board area by >60% while meeting IEEE 802.3 and PCIe jitter masks. |
Use Scenario: Server motherboard or accelerator card with multiple PCIe root complexes, switches, and endpoints. IC Role / Device Role / Timing Role: Common clock source delivering Gen 3 SRNS-compliant and Gen 4-compliant clocks to all PCIe slots and controllers. Use Value: Ensures deterministic link training and stable Gen 4 x16 lanes via <0.32 ps RMS jitter and loss-of-lock monitoring. |
| Broadcast Video/Audio Sync | FPGA & Processor Clocking |
Use Scenario: SMPTE ST 2082/2081 video transport system requiring precise 27 MHz, 74.25 MHz, and 148.5 MHz timing across HD/4K/8K signal paths. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating exact broadcast-standard frequencies with zero ppm error and <10 ps cycle-cycle jitter. Use Value: Enables frame-accurate genlock across multi-channel video pipelines without external dividers or jitter cleaners. |
Use Scenario: Heterogeneous compute platform integrating FPGA fabric, ARM SoC, DDR4 memory, and high-speed SerDes. IC Role / Device Role / Timing Role: Centralized clock hub supplying 100 MHz processor clock, 200 MHz DDR4 clock, 156.25 MHz SerDes reference, and 25 MHz debug clock. Use Value: Simplifies BOM and layout with one device replacing multiple oscillators and buffers while maintaining <0.7 ps RMS jitter on all domains. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output programmable clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D08189-GM | Higher integration: 8 outputs, integrated LDOs, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency. | Targeted at JESD204B data converter systems and multi-FPGA synchronization where deterministic delay matters. | Select when needing >4 outputs, tighter jitter, or deterministic latency; not drop-in due to different pinout and register map. |
| ICS8430I-01T | Fixed-frequency quad LVDS generator (no I²C programming); 0.9 ps RMS jitter; no spread spectrum or phase adjust. | Suitable only for static clock trees where frequencies never change post-BOM. | Choose for cost-sensitive, fixed-clock applications where programmability and flexibility are unnecessary. |
Compared with Si5332A-D08189-GM and ICS8430I-01T, the SI5338Q-B04069-GM offers optimal balance of programmability, jitter performance, and pin compatibility within the Si5338 family-making it ideal for PCIe, Ethernet, and broadcast systems requiring field-upgradable timing without redesign.
Availability
SI5338Q-B04069-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server boards, 10GbE switching platforms, and broadcast video timing systems requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for SI5338Q-B04069-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and industrial markets.
The SI5338 product line was designed to replace multiple fixed-frequency oscillators with a single, software-configurable clock generator for high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and broadcast video-while maintaining ultra-low jitter and industrial temperature reliability.
FAQ
What is the primary function of the SI5338Q-B04069-GM in a PCIe Gen 4 system?
The SI5338Q-B04069-GM serves as the common clock source for PCIe Gen 4 root complexes and endpoints, delivering compliant 100 MHz clocks with ≤0.45 ps RMS jitter (measured per PCIe Base Spec 4.0). Its dual-stage PLL and MultiSynth™ architecture ensure stable lock under dynamic load conditions, and its INTR pin provides real-time loss-of-lock detection critical for system diagnostics. SI5338Q-B04069-GM supports both common clock and SRNS modes per specification.
Does the SI5338Q-B04069-GM support spread-spectrum clocking (SSC), and how is it configured?
Yes, the SI5338Q-B04069-GM supports fully programmable spread-spectrum clocking on any output: spread range 0.5–5.0%, modulation rate 33–63 kHz, and applicable to frequencies from 5 to 350 MHz. SSC is configured via I²C registers (e.g., registers 135–137) or through ClockBuilder Pro software. The default setting is ~0.5% down-spread at ~31.5 kHz. SI5338Q-B04069-GM allows independent SSC enable/disable per output channel.
Can the SI5338Q-B04069-GM generate four different frequencies simultaneously, and what are the limits?
Yes, the SI5338Q-B04069-GM synthesizes four independent frequencies simultaneously using its four MultiSynth™ engines. Each output supports 0.16–710 MHz, but only two unique frequencies above 350 MHz may be active concurrently (Fvco/4 and Fvco/6). All outputs achieve true zero-ppm accuracy with 1 ppb resolution. SI5338Q-B04069-GM maintains <0.7 ps RMS jitter even with mixed-frequency configurations.
What input references does the SI5338Q-B04069-GM accept, and are external components required?
The SI5338Q-B04069-GM accepts crystal (8–30 MHz, requiring no external load caps for 12 pF CL), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) inputs. For differential inputs (IN1/IN2, IN5/IN6), a 100 Ω external termination resistor is required. Single-ended inputs (IN3/IN4) need no external components beyond standard decoupling. SI5338Q-B04069-GM integrates on-chip crystal load capacitance (11–13 pF) and supports register tuning for 17–19 pF crystals.
How is output voltage level controlled on the SI5338Q-B04069-GM, and can different outputs run at different voltages?
Each of the four output banks (VDDO0–VDDO3) has an independent supply pin, allowing SI5338Q-B04069-GM to drive LVPECL (2.5/3.3 V), LVDS (1.8/2.5/3.3 V), HCSL (1.8 V), or CMOS (1.5/1.8/2.5/3.3 V) loads simultaneously at different voltage levels. Output driver voltage is set by the applied VDDOn supply-not by register configuration-enabling true mixed-voltage clock distribution without level shifters. SI5338Q-B04069-GM supports 1.4–3.63 V per VDDOn pin.
SI5338Q-B04069-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338Q-B04069-GM FAQ
1.How can I place an order for SI5338Q-B04069-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338Q-B04069-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338Q-B04069-GM reliable?
The price and inventory of SI5338Q-B04069-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338Q-B04069-GM is usually 5 days.
3.What payment methods are accepted for SI5338Q-B04069-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338Q-B04069-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338Q-B04069-GM?
SI5338Q-B04069-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338Q-B04069-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338Q-B04069-GM?
For technical support, including SI5338Q-B04069-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338Q-B04069-GM requirements.
6.How does Aetrix verify that SI5338Q-B04069-GM is sourced from the original manufacturer or authorized distributors?
All SI5338Q-B04069-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338Q-B04069-GM meets industry standards.
7.What is the process for return or replacement of SI5338Q-B04069-GM?
All SI5338Q-B04069-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338Q-B04069-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338Q-B04069-GM part is unused and in its original packaging.
Return procedure for SI5338Q-B04069-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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