Skyworks Solutions Inc. SI5338Q-B04071-GMR
- Part No.:
- SI5338Q-B04071-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338Q-B04071-GMR.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338Q-B04071-GMR from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing.
For engineers reviewing the SI5338Q-B04071-GMR datasheet, SI5338Q-B04071-GMR pinout, SI5338Q-B04071-GMR application, or SI5338Q-B04071-GMR equivalent, key selection criteria include PCIe Gen 4 common-clock jitter (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ fractional synthesis resolution (1 ppb), spread-spectrum control (0.5–5.0% down-spread), and loss-of-lock/loss-of-signal alarm support.
Technical Context
The SI5338Q-B04071-GMR implements a two-stage PLL architecture: a high-stability integer-N Phase-Locked Loop (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesis blocks (Stage 2) generating each output. Each MultiSynth supports integer or fractional mode with programmable initial phase offset (±45 ns) and glitchless frequency increment/decrement (1 ppm steps).
Output drivers are fully decoupled-each supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats across overlapping frequency ranges (e.g., LVDS: 0.16–350 MHz; CMOS: 0.16–200 MHz), with independent VDDO supplies (1.4–3.63 V) and configurable slew rate, duty cycle, and termination. The device operates across –40 to +85 °C and supports external feedback for zero-delay mode.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common-clock jitter spec (≤0.45 ps RMS) |
| Output Count & Type | Four configurable outputs: up to 4 differential (LVPECL/LVDS/HCSL/CML) or 8 single-ended (CMOS/SSTL/HSTL), or mixed |
| Frequency Range | 0.16–710 MHz per output; supports >350 MHz on two outputs simultaneously (Fvco/4 and Fvco/6) |
| Input Reference Support | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Supply Voltages | Core: 1.8/2.5/3.3 V ± tolerance; Output buffers: independently selectable 1.5/1.8/2.5/3.3 V per driver |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad |
| Operating Temperature | –40 °C to +85 °C ambient; qualified per industrial temperature grade |
Pinout & Package
SI5338Q-B04071-GMR is housed in a 24-lead, 4 × 4 mm QFN package with wettable flank leads and an exposed thermal pad (pin 24). Pin 1 is top-left corner (IN1), with pins numbered counterclockwise. The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential input pairs | Accept AC-coupled differential clocks up to 710 MHz; require external 100 Ω termination |
| IN3, IN4 | Single-ended input pins | Support CMOS/SSTL/HSTL inputs (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A–CLK3B | Differential output pairs | Four independent output channels (CLK0–CLK3), each with A/B complementary pins; format and voltage configurable per channel |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.4–3.63 V supplies per output bank; enable level translation between domains |
| VDD | Core supply | Single 1.8/2.5/3.3 V supply for PLL, logic, and memory; PSRR optimized for noise immunity |
| SCL, SDA | I²C/SMBus interface | Standard 100/400 kHz operation; supports ClockBuilder Pro programming and runtime configuration |
| INTR | Interrupt output | Open-drain status indicator for loss-of-lock (LOL) and loss-of-signal (LOS) events |
| RSVD_GND | Reserved ground | Internal test pin; must be connected to GND per layout guidelines |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Four independent fractional-N synthesizers enabling true zero-ppm accuracy on all outputs with 1 ppb resolution |
| PCIe Gen 4 compliance | Meets Common Clock jitter spec (0.15–0.45 ps RMS) and SRNS requirements without external filtering |
| Glitchless frequency tuning | Pin-controlled or I²C-based frequency increment/decrement in 1 ppm steps with <667 ns update time |
| Programmable phase alignment | ±45 ns initial phase offset per output with <20 ps step resolution and sub-nanosecond skew control |
| Spread-spectrum clocking | Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) on any output to reduce EMI |
| Zero-delay mode support | External feedback path enables synchronous clock distribution with minimal propagation delay variation |
Applications
| PCIe Gen 4 Switch Timing | Ethernet Switch/Routing |
|---|---|
Use Scenario: Providing synchronized reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric card. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent 100 MHz HCSL clocks with <0.45 ps RMS jitter and matched phase alignment. Use Value: Enables full Gen 4 lane compliance without external jitter cleaners; eliminates need for four discrete oscillators and reduces board area by >60%. |
Use Scenario: Generating multi-rate clocks (125 MHz, 156.25 MHz, 312.5 MHz) for 1/10/25 GbE PHYs and packet processors in a modular switch line card. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing precise Ethernet-compliant frequencies from a single 25 MHz crystal reference. Use Value: Reduces BOM count and simplifies clock tree design while supporting IEEE 802.3bj/802.3by jitter masks via programmable SSC. |
| Broadcast Video Timing | FPGA Processor Clocking |
Use Scenario: Delivering SMPTE ST 2082 (12G-SDI) and ST 2081 (6G-SDI) reference clocks to video encoder/decoder FPGAs in broadcast infrastructure. IC Role / Device Role / Timing Role: Low-jitter clock source generating 74.25 MHz, 148.5 MHz, and 297 MHz outputs with <10 ps pk-pk period jitter. Use Value: Ensures bit-error-free transmission over long coaxial runs by meeting SMPTE RP 184 jitter limits without post-synthesis cleanup. |
Use Scenario: Supplying core, I/O, and transceiver reference clocks to Xilinx Versal or Intel Agilex FPGAs in adaptive compute acceleration platforms. IC Role / Device Role / Timing Role: Configurable quad generator providing 300 MHz (core), 100 MHz (DDR4), 156.25 MHz (PCIe), and 250 MHz (GTYP) clocks from one device. Use Value: Eliminates inter-chip skew and simplifies power sequencing by integrating multiple clock domains with independent voltage control. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D06189-GM | Higher integration: 8 outputs, integrated LDOs, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency | Targeted at JESD204B SerDes, radar, and 5G wireless where sub-0.5 ps jitter and deterministic delay are mandatory | Select when needing >4 outputs, tighter jitter, or JESD204B synchronization; requires different PCB layout and ClockBuilder configuration |
| ICS8430I-01T | Fixed-frequency, non-programmable quad LVDS generator; 1.2 ps RMS jitter; no I²C interface or MultiSynth flexibility | Used in cost-sensitive, static-clock applications like legacy storage controllers where frequency agility is unnecessary | Select only for fixed-frequency deployments requiring minimal firmware overhead; lacks PCIe Gen 4 compliance and spread-spectrum capability |
Compared with Si5332A-D06189-GM, SI5338Q-B04071-GMR offers lower system cost and simpler configuration for PCIe/Ethernet applications, while ICS8430I-01T provides lower unit cost but sacrifices programmability, jitter performance, and Gen 4 readiness.
Availability
SI5338Q-B04071-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, and broadcast video timing requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for SI5338Q-B04071-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with broad portfolio coverage and high-reliability manufacturing.
The Si5338 family was designed for high-performance, multi-protocol clock generation in data center, telecom, and broadcast systems-enabling consolidation of discrete oscillators into a single programmable, low-jitter timing IC.
FAQ
What is the maximum output frequency supported by SI5338Q-B04071-GMR?
The SI5338Q-B04071-GMR supports up to 710 MHz on LVPECL/LVDS outputs, though only two unique frequencies above 350 MHz can be generated simultaneously (Fvco/4 and Fvco/6). For example, it can deliver 710 MHz and 550 MHz concurrently, but not three distinct >350 MHz clocks. This limitation arises from the internal VCO frequency division architecture and is documented in Section 3.3 of the datasheet.
Does SI5338Q-B04071-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?
Yes, SI5338Q-B04071-GMR is compliant with PCIe Gen 4 SRNS requirements, achieving 0.11–0.32 ps RMS jitter under specified conditions (PLL bandwidth 2–4 MHz, CDR = 10 MHz). This is verified using the Skyworks PCIe Clock Jitter Tool and conforms to PCI Express Base Specification 4.0 rev. 0.5. Configuration requires proper register settings for loop bandwidth and feedback path selection.
Can SI5338Q-B04071-GMR generate different output voltages on each channel?
Yes, SI5338Q-B04071-GMR supports independent output supply voltages per channel via VDDO0–VDDO3 pins, allowing simultaneous operation at 1.5 V (HCSL), 1.8 V (LVDS), 2.5 V (SSTL), and 3.3 V (CMOS) on CLK0–CLK3 respectively. This enables direct interfacing with mixed-voltage SoCs, FPGAs, and PHYs without external level shifters.
How is SI5338Q-B04071-GMR programmed, and is ClockBuilder Pro required?
SI5338Q-B04071-GMR is programmed via its I²C/SMBus interface (SCL/SDA pins) using register writes. While ClockBuilder Pro is the official Skyworks GUI tool for configuration and .c file generation, custom firmware can directly write to registers using documented addresses and bit fields. Factory pre-programming is also available for turnkey deployment.
What thermal considerations apply to SI5338Q-B04071-GMR in continuous operation?
SI5338Q-B04071-GMR has a junction-to-ambient thermal resistance (θJA) of 37 °C/W in still air. At full load (45 mA core current, 30 mA per active LVPECL output), power dissipation reaches ~225 mW. To maintain TJ ≤125 °C, PCB layout must include adequate copper pour under the exposed thermal pad and minimize ambient temperature rise-especially in enclosed industrial enclosures.
SI5338Q-B04071-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338Q-B04071-GMR FAQ
1.How can I place an order for SI5338Q-B04071-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338Q-B04071-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338Q-B04071-GMR reliable?
The price and inventory of SI5338Q-B04071-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338Q-B04071-GMR is usually 5 days.
3.What payment methods are accepted for SI5338Q-B04071-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338Q-B04071-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338Q-B04071-GMR?
SI5338Q-B04071-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338Q-B04071-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338Q-B04071-GMR?
For technical support, including SI5338Q-B04071-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338Q-B04071-GMR requirements.
6.How does Aetrix verify that SI5338Q-B04071-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338Q-B04071-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338Q-B04071-GMR meets industry standards.
7.What is the process for return or replacement of SI5338Q-B04071-GMR?
All SI5338Q-B04071-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338Q-B04071-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338Q-B04071-GMR part is unused and in its original packaging.
Return procedure for SI5338Q-B04071-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5338Q-B04071-GMR Tags

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