Skyworks Solutions Inc. SI5338Q-B04074-GM
- Part No.:
- SI5338Q-B04074-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338Q-B04074-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338Q-B04074-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis, delivering four independent low-jitter clocks (0.7 ps RMS typ), PCIe Gen 1–4 and SRNS-compliant outputs, and configurable LVPECL/LVDS/HCSL/CMOS signal formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed networking and FPGA timing applications.
For engineers reviewing the SI5338Q-B04074-GM datasheet, SI5338Q-B04074-GM pinout, SI5338Q-B04074-GM application, or SI5338Q-B04074-GM equivalent, key selection criteria include PCIe Gen 4 common-clock jitter compliance (0.15–0.45 ps RMS), independent per-output voltage control (1.5/1.8/2.5/3.3 V), 24-QFN package footprint, and I²C/SMBus programmability with ClockBuilder Pro support.
Technical Context
The SI5338Q-B04074-GM implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. This enables true zero-ppm frequency accuracy and <20 ps phase step resolution on all four outputs.
It supports flexible input references - 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential - and offers independent spread-spectrum control (0.5–5.0% spread, 33–63 kHz modulation) on any output, plus loss-of-lock and loss-of-signal alarms for system monitoring.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common-clock jitter spec (≤0.45 ps RMS). |
| Output Count & Type | Four differential outputs (CLK0A/B through CLK3A/B); supports LVPECL, LVDS, HCSL, CML, SSTL, HSTL, CMOS. |
| Frequency Range | 0.16–710 MHz per output; integer/fractional synthesis with 1 ppb resolution. |
| Supply Voltages | Core: 1.8 / 2.5 / 3.3 V; independent output buffers: 1.5 / 1.8 / 2.5 / 3.3 V per driver. |
| Interface | I²C/SMBus-compatible serial interface; programmable via ClockBuilder Pro software. |
| Operating Temp | –40 °C to +85 °C ambient; qualified for industrial and telecom line card environments. |
| Package | 24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch; exposed thermal pad for thermal management. |
Pinout & Package
SI5338Q-B04074-GM uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family specification.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2 | Differential input pair | Accepts 5–710 MHz AC-coupled differential reference; requires external 100 Ω termination. |
| IN3, IN4 | Single-ended input pair | Supports 5–200 MHz CMOS-level clocks; VIH = 0.7×VDD, VIL = 0.3×VDD. |
| CLK0A–CLK3B | Differential output pairs | Four independent output drivers; each configurable for format, voltage, and slew rate. |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.5/1.8/2.5/3.3 V rails per output group; decoupling required per output domain. |
| VDD | Core supply | Single 1.8/2.5/3.3 V core rail; PSRR optimized for noise immunity in mixed-signal systems. |
| SCL, SDA | I²C interface | Standard SMBus-compatible bus; supports 100 kHz / 400 kHz / 1 MHz modes; pull-ups required. |
| INTR | Interrupt output | Open-drain status flag for loss-of-lock or loss-of-signal events; active-low assertion. |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Four independent fractional-N synthesizers enable simultaneous, arbitrary-frequency generation with 0 ppm error and <20 ps phase step resolution. |
| PCIe Gen 4 compliance | Meets Common Clock jitter requirement (0.15–0.45 ps RMS) and SRNS mode for Gen 3, enabling drop-in use in server and switch designs. |
| Configurable spread spectrum | Per-output SSC with user-selectable spread (0.5–5.0%), modulation rate (33–63 kHz), and direction (down/up/center); reduces EMI without affecting timing margin. |
| Glitchless frequency tuning | Independent FINC/FDEC pins allow real-time, sub-ppm frequency adjustment (1 ppm steps) without output interruption or phase discontinuity. |
| Flexible input support | Five input options: crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz); eliminates need for external buffers or level shifters. |
Applications
| PCIe Gen 4 Switch Timing | Ethernet Switch/Routing |
|---|---|
Use Scenario: High-density 32-lane PCIe Gen 4 switch ASIC requiring synchronized, low-jitter reference clocks for SerDes lanes and management logic. IC Role / Device Role / Timing Role: Primary clock generator providing four independent 100 MHz HCSL clocks with PCIe Gen 4 common-clock jitter compliance (≤0.45 ps RMS). Use Value: Eliminates four discrete oscillators; enables single-chip timing solution with deterministic skew (<100 ps) and programmable SSC to meet FCC Class A emissions limits. |
Use Scenario: 10 GbE/25 GbE line card with multi-port Ethernet PHYs and packet processors needing multiple synchronized clocks at 125 MHz, 156.25 MHz, and 312.5 MHz. IC Role / Device Role / Timing Role: Quad-output clock source generating LVDS and HCSL clocks with independent voltage control (1.8 V/2.5 V) per PHY interface. Use Value: Supports heterogeneous PHY voltage requirements on one chip; phase alignment capability ensures deterministic inter-PHY skew for time-sensitive packet forwarding. |
| FPGA & SoC Clocking | Broadcast Video Timing |
Use Scenario: Xilinx Versal or Intel Agilex FPGA board requiring separate clocks for PL fabric, memory interfaces (DDR4), transceivers, and subsystem peripherals. IC Role / Device Role / Timing Role: Configurable clock generator delivering 300 MHz LVDS (transceivers), 133 MHz LVCMOS (DDR4), 100 MHz HCSL (PCIe), and 25 MHz CMOS (peripherals) from one device. Use Value: Reduces BOM count and PCB area vs. discrete oscillators; I²C reprogramming allows runtime clock reconfiguration during FPGA bitstream updates. |
Use Scenario: SMPTE ST 2110 IP video router requiring precise 27 MHz, 74.25 MHz, and 148.5 MHz reference clocks with sub-nanosecond phase stability for frame synchronization. IC Role / Device Role / Timing Role: Low-jitter (0.7 ps RMS) quad generator producing three video-grade clocks plus spare for auxiliary functions, all traceable to same crystal reference. Use Value: Achieves broadcast-grade timing accuracy without external jitter cleaners; independent phase offset control enables fine-grained frame alignment across distributed endpoints. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D05989-GM | Higher integration: 8 outputs, integrated jitter cleaner, lower jitter (0.35 ps RMS), but larger 32-QFN package and higher cost. | Targeted at ultra-low-jitter infrastructure (5G fronthaul, optical transport) where >4 outputs or <0.4 ps RMS is mandatory. | Select when >4 outputs or sub-0.4 ps RMS jitter is required; not pin-compatible with SI5338Q-B04074-GM. |
| ICS8430I-01T | Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; 3.3 V only; no spread spectrum or phase control. | Suitable for cost-sensitive, static-clock applications like legacy PCIe Gen 2 or SATA timing where reprogrammability is unnecessary. | Choose for non-reconfigurable, high-volume applications where programmability and advanced features are not needed. |
Compared with Si5332A-D05989-GM and ICS8430I-01T, the SI5338Q-B04074-GM uniquely balances programmability, PCIe Gen 4 compliance, and compact 24-QFN packaging - making it optimal for space-constrained, field-upgradable networking and FPGA platforms where flexibility and jitter performance must coexist.
Availability
SI5338Q-B04074-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, and FPGA/SoC clocking requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for SI5338Q-B04074-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.
The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed digital systems - designed specifically for PCIe, Ethernet, broadcast video, and FPGA applications demanding precision timing in compact footprints.
FAQ
What is the maximum output frequency supported by the SI5338Q-B04074-GM?
The SI5338Q-B04074-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 250 MHz on HCSL, and 200 MHz on CMOS. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) due to VCO architecture constraints. All outputs maintain 0.7 ps RMS jitter at rated frequencies when using low-noise differential inputs.
Does the SI5338Q-B04074-GM support PCIe Gen 4 Common Clock compliance?
Yes, the SI5338Q-B04074-GM is explicitly validated for PCIe Gen 4 Common Clock operation with ≤0.45 ps RMS jitter (10 kHz–50 MHz band) and meets SRNS requirements for Gen 3. This is confirmed in Skyworks' Table 12 and AN562 documentation using 100 MHz HCSL outputs and standard PCIe jitter measurement methodology.
Can the SI5338Q-B04074-GM generate different output voltages on each channel?
Yes - the SI5338Q-B04074-GM provides independent VDDO0–VDDO3 supply pins, allowing each of its four output drivers to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage PHYs (e.g., 1.8 V Ethernet PHY + 2.5 V DDR controller) without external level shifters.
How is the SI5338Q-B04074-GM programmed, and is firmware required?
The SI5338Q-B04074-GM is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software, which generates configuration files and registers settings. No external firmware or microcontroller is required - the device stores settings in one-time-programmable (OTP) NVM and boots preconfigured. Field updates are supported over I²C.
What package type and thermal characteristics does the SI5338Q-B04074-GM have?
The SI5338Q-B04074-GM uses a 24-pin QFN package (4 mm × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Its thermal resistance is θJA = 37 °C/W (still air) and θJC = 10 °C/W, supporting operation up to +85 °C ambient with standard PCB copper pour and thermal vias under the pad.
SI5338Q-B04074-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338Q-B04074-GM FAQ
1.How can I place an order for SI5338Q-B04074-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338Q-B04074-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338Q-B04074-GM reliable?
The price and inventory of SI5338Q-B04074-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338Q-B04074-GM is usually 5 days.
3.What payment methods are accepted for SI5338Q-B04074-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338Q-B04074-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338Q-B04074-GM?
SI5338Q-B04074-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338Q-B04074-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338Q-B04074-GM?
For technical support, including SI5338Q-B04074-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338Q-B04074-GM requirements.
6.How does Aetrix verify that SI5338Q-B04074-GM is sourced from the original manufacturer or authorized distributors?
All SI5338Q-B04074-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338Q-B04074-GM meets industry standards.
7.What is the process for return or replacement of SI5338Q-B04074-GM?
All SI5338Q-B04074-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338Q-B04074-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338Q-B04074-GM part is unused and in its original packaging.
Return procedure for SI5338Q-B04074-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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