Skyworks Solutions Inc. SI5338Q-B04075-GM
- Part No.:
- SI5338Q-B04075-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338Q-B04075-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338Q-B04075-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in Ethernet switch/router, FPGA clocking, and PCIe timing systems.
For engineers reviewing the SI5338Q-B04075-GM datasheet, SI5338Q-B04075-GM pinout, SI5338Q-B04075-GM application, or SI5338Q-B04075-GM equivalent, key selection criteria include output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL), independent per-output voltage (1.5/1.8/2.5/3.3 V), any-frequency synthesis down to 0.16 MHz, spread-spectrum control, and I²C/SMBus programmability via ClockBuilder Pro.
Technical Context
The SI5338Q-B04075-GM implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each MultiSynth supports integer or fractional mode, enabling true zero-ppm frequency accuracy and <20 ps phase step resolution.
Its output stage provides per-driver supply voltage selection (VDDO0–VDDO3), independent enable/disable (OEB), glitchless frequency increment/decrement in 1 ppm steps, and programmable initial phase offset (±45 ns). The device supports external feedback for zero-delay mode and includes loss-of-lock and loss-of-signal alarms with interrupt output (INTR).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps - meets PCIe Gen 3 SRNS and GbE jitter requirements with LVDS/HCSL outputs |
| Output Frequency Range | 0.16–710 MHz - supports LVPECL/LVDS (≤710 MHz), HCSL (≤250 MHz), CMOS (≤200 MHz), SSTL/HSTL (≤350 MHz) |
| Input Reference Support | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - enables flexible system clock sourcing |
| Supply Voltages | VDD = 1.8/2.5/3.3 V; VDDOx = 1.4–3.63 V - allows mixed-voltage board design with independent output driver biasing |
| Package | 24-pin QFN, 4 × 4 mm - space-efficient footprint compatible with automated SMT assembly and thermal management (θJA = 37 °C/W) |
| Operating Temperature | –40 to +85 °C - qualified for industrial and telecom line card environments without derating |
| I²C Interface | SMBus-compatible, 100 kHz/400 kHz - enables configuration and monitoring without dedicated programming hardware |
Pinout & Package
SI5338Q-B04075-GM is housed in a 4 × 4 mm, 24-lead QFN package with exposed thermal pad (pin 24). Pin assignments are fixed per the Si5338 family: inputs IN1–IN6 support differential/single-ended reference clocks; outputs CLK0A/B through CLK3A/B provide four differential pairs; VDDO0–VDDO3 supply independent output driver rails; SCL/SDA/INTR enable I²C control and status reporting.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential Input Pair | Accepts AC-coupled 5–710 MHz differential clock; requires external 100 Ω termination |
| IN3, IN4 | Single-Ended Input | Supports CMOS/SSTL/HSTL 5–350 MHz; VIH/VIL referenced to VDD |
| CLK0A–CLK3B | Differential Output Pair | Four independent LVPECL/LVDS/HCSL/CML outputs; each pair shares VDDOx rail |
| VDDO0–VDDO3 | Output Driver Supply | Per-output voltage selection (1.5/1.8/2.5/3.3 V); decoupling required per output group |
| SCL, SDA, INTR | I²C Control Interface | SMBus-compatible bus interface with open-drain INTR for lock/LOS event signaling |
| VDD, GND, RSVD_GND | Core Power & Ground | 1.8/2.5/3.3 V core supply; multiple GND pins and thermal pad ensure low-noise power delivery |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ Synthesis | Four independent fractional-N synthesizers deliver any-frequency outputs from 0.16 MHz to 710 MHz with 0 ppm error in integer mode |
| PCIe Compliance | Fully compliant with PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS specifications, verified using Intel Clock Jitter Tool |
| Glitchless Frequency Tuning | Independent FINC/FDEC pins enable real-time 1 ppm-step frequency adjustment without output interruption |
| Programmable Phase Offset | ±45 ns initial phase shift per output with <20 ps step resolution-enables precise inter-channel skew alignment |
| Spread Spectrum Control | Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, 5–350 MHz range-reduces EMI in dense PCB layouts |
Applications
| Ethernet Switch/Router Timing | PCIe Gen 3/4 Clocking |
|---|---|
|
Use Scenario: High-port-count 1/10 GbE switches requiring synchronized, low-jitter clocks for SerDes lanes and packet processing subsystems. IC Role / Device Role / Timing Role: Quad clock generator providing independent 125 MHz, 156.25 MHz, and 250 MHz outputs with matched phase alignment across PHY and MAC domains. Use Value: Meets PCIe Gen 3 SRNS and IEEE 802.3ap jitter limits (0.11–0.32 ps RMS), eliminating need for multiple discrete oscillators and reducing BOM count by 75%. |
Use Scenario: Server motherboard with dual x16 PCIe Gen 4 slots, CPU interconnect, and NVMe storage controllers demanding strict common-clock jitter compliance. IC Role / Device Role / Timing Role: Single-chip source for 100 MHz PCIe refclk, 100 MHz CPU QPI/UPI clock, and two auxiliary clocks-all synthesized from one 25 MHz crystal. Use Value: Achieves 0.15–0.45 ps RMS jitter per PCIe Gen 4 spec under common-clock topology, validated with Skyworks PCIe Clock Jitter Tool and Intel reference methodology. |
| Broadcast Video/Audio Timing | FPGA & Processor Clocking |
|
Use Scenario: SMPTE ST 2082/2081 video transport equipment requiring genlock-capable, ultra-low-jitter clocks for 12G-SDI, HDMI 2.1, and audio sample rate conversion. IC Role / Device Role / Timing Role: Configurable buffer and frequency translator delivering 74.25 MHz, 148.5 MHz, and 297 MHz with sub-20 ps inter-output skew. Use Value: Supports SMPTE RP184 jitter mask via 0.7 ps RMS phase noise floor and programmable phase offset-enabling frame-accurate synchronization across multi-channel video pipelines. |
Use Scenario: Industrial FPGA-based motion controller with ARM Cortex-A9 processor, DDR3 memory, and real-time I/O interfaces needing isolated, voltage-flexible clocks. IC Role / Device Role / Timing Role: Central timing hub supplying 50 MHz processor clock, 400 MHz DDR3 interface clock, 100 MHz peripheral bus clock, and 10 MHz watchdog timer-all from one device. Use Value: Independent VDDOx rails allow 1.8 V for DDR3, 3.3 V for peripherals, and 1.5 V for FPGA I/O banks-eliminating level-shifter ICs and simplifying power sequencing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D06189-GM | Higher integration: 8 outputs, integrated EEPROM, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency | Targeted at JESD204B-compliant data converters and 5G wireless infrastructure where deterministic delay matters | Choose when >4 outputs, embedded configuration storage, or sub-0.4 ps jitter is required-requires layout revision due to 5 × 5 mm 32-QFN package |
| ICS8430I-01T | Fixed-frequency, non-programmable quad LVDS generator; no I²C interface; higher jitter (1.2 ps RMS); 3.3 V only | Suitable for cost-sensitive, static-clock applications like legacy telecom line cards with unchanging frequency plans | Choose only if frequency plan is immutable and I²C programmability is unnecessary-no firmware or ClockBuilder Pro dependency |
Compared with SI5338Q-B04075-GM, the Si5332A offers superior jitter and configurability but demands larger board area and higher cost, while the ICS8430I sacrifices flexibility and performance for simplicity and unit cost-making SI5338Q-B04075-GM the optimal balance for programmable, multi-standard timing in space-constrained industrial designs.
Availability
SI5338Q-B04075-GM is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 3/4 clocking, and broadcast video/audio timing requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for SI5338Q-B04075-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.
The Si5338 product line delivers highly configurable, low-jitter clock generation for high-speed serial interfaces-including PCIe, Ethernet, Fibre Channel, and broadcast video-designed to replace multiple discrete oscillators with a single programmable IC.
FAQ
What is the primary function of the SI5338Q-B04075-GM in a timing architecture?
The SI5338Q-B04075-GM serves as an I²C-programmable quad clock generator that synthesizes up to four independent, any-frequency output clocks from a single reference input. Its MultiSynth™ architecture enables zero-ppm precision, making SI5338Q-B04075-GM ideal for replacing multiple crystal oscillators in PCIe, Ethernet, and FPGA systems while maintaining tight jitter and phase alignment specifications.
Does the SI5338Q-B04075-GM support PCIe Gen 4 Common Clock compliance?
Yes, the SI5338Q-B04075-GM meets PCIe Gen 4 Common Clock jitter requirements with 0.15–0.45 ps RMS (10 kHz–50 MHz) when configured per Skyworks' validated reference design and measured using the Intel Clock Jitter Tool. This compliance is explicitly documented in the Si5338 datasheet Rev. 1.6, Table 12, and confirmed via Skyworks' PCIe Clock Jitter Tool.
Can the SI5338Q-B04075-GM generate different output voltages on each channel?
Yes, the SI5338Q-B04075-GM supports independent output supply rails (VDDO0–VDDO3), allowing each of its four output drivers to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage components-such as 1.8 V FPGAs, 3.3 V microcontrollers, and 1.5 V DDR memory-without external level shifters, a capability confirmed in the Si5338 datasheet Section 1.1 and Table 1.
How is the SI5338Q-B04075-GM programmed and configured?
The SI5338Q-B04075-GM is programmed via its I²C/SMBus-compatible serial interface using Skyworks' ClockBuilder Pro software. This GUI tool generates custom configuration files, validates timing constraints, and writes settings directly to the device's internal NVM or RAM. Configuration can also be performed in-system via microcontroller firmware, as detailed in Si5338 datasheet Sections 5 and 6.
What package type and thermal characteristics does the SI5338Q-B04075-GM have?
The SI5338Q-B04075-GM uses a 4 × 4 mm, 24-lead QFN package with exposed thermal pad (pin 24). Its thermal resistance is θJA = 37 °C/W (still air), and θJC = 10 °C/W, enabling reliable operation at full load across –40 to +85 °C ambient. The package is RoHS-compliant and qualified per JEDEC standards, as specified in Si5338 datasheet Section 9 and Table 4.
SI5338Q-B04075-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338Q-B04075-GM FAQ
1.How can I place an order for SI5338Q-B04075-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338Q-B04075-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338Q-B04075-GM reliable?
The price and inventory of SI5338Q-B04075-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338Q-B04075-GM is usually 5 days.
3.What payment methods are accepted for SI5338Q-B04075-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338Q-B04075-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338Q-B04075-GM?
SI5338Q-B04075-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338Q-B04075-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338Q-B04075-GM?
For technical support, including SI5338Q-B04075-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338Q-B04075-GM requirements.
6.How does Aetrix verify that SI5338Q-B04075-GM is sourced from the original manufacturer or authorized distributors?
All SI5338Q-B04075-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338Q-B04075-GM meets industry standards.
7.What is the process for return or replacement of SI5338Q-B04075-GM?
All SI5338Q-B04075-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338Q-B04075-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338Q-B04075-GM part is unused and in its original packaging.
Return procedure for SI5338Q-B04075-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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