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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338Q-B04075-GMR

Name: SI5338Q-B04075-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338Q-B04075-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338Q-B04075-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338Q-B04075-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338Q-B04075-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independent differential output drivers, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in Ethernet switch/router and FPGA clocking systems.

For engineers reviewing the SI5338Q-B04075-GMR datasheet, SI5338Q-B04075-GMR pinout, SI5338Q-B04075-GMR application, or SI5338Q-B04075-GMR equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis, independent per-output voltage (1.5/1.8/2.5/3.3 V), 24-pin 4×4 mm QFN package, and I²C/SMBus programmability with ClockBuilder Pro software support.

Technical Context

The SI5338Q-B04075-GMR implements a two-stage PLL architecture: a high-stability input stage with configurable reference inputs (8–30 MHz crystal, 5–710 MHz differential, or 5–350 MHz single-ended), followed by four independent MultiSynth™ fractional-N synthesis blocks. Each output driver operates with its own R, M, and P dividers, enabling true zero-ppm frequency accuracy on all four outputs simultaneously.

It supports flexible configuration modes including free-running clock generation, synchronous frequency translation, and clock buffer mode (PLL bypass) with sub-0.2 ps RMS additive jitter. Status monitoring includes loss-of-lock and loss-of-signal alarms, while dynamic control features include independent 1 ppm frequency increment/decrement and <20 ps phase step resolution per output.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements
Output Frequency Range	0.16–710 MHz per channel; supports LVPECL/LVDS (≤710 MHz), HCSL (≤250 MHz), CMOS (≤200 MHz), SSTL/HSTL (≤350 MHz)
Input Reference Support	External crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, halogen-free, moisture sensitivity level 3
Operating Temperature	–40 °C to +85 °C ambient; qualified per industrial temperature grade specifications
Power Consumption	45 mA typical core supply current at 100 MHz on all outputs with 25 MHz reference clock

Pinout & Package

SI5338Q-B04075-GMR is housed in a 24-pin, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow Skyworks' standard Si5338 pinout: dual differential inputs (IN1/IN2, IN5/IN6), two single-ended inputs (IN3, IN4), four differential output pairs (CLK0A/B through CLK3A/B), six VDDOx power pins (VDDO0–VDDO3), one core VDD, two I²C lines (SCL, SDA), interrupt output (INTR), and ground connections.

Pin/Terminal	Circuit Role	Design Meaning
IN1 / IN2	Differential reference input pair	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination
IN3 / IN4	Single-ended reference inputs	Support CMOS/SSTL/HSTL signals (5–350 MHz); each configurable as independent reference source
CLK0A / CLK0B – CLK3A / CLK3B	Differential clock outputs (4 pairs)	Individually configurable format (LVPECL/LVDS/HCSL/CML), frequency, voltage, and phase
VDDO0 – VDDO3	Output buffer supply rails	Independent 1.5/1.8/2.5/3.3 V supplies per output bank; enables mixed-voltage system interfacing
SCL / SDA	I²C/SMBus interface	Standard 100 kHz / 400 kHz operation; supports ClockBuilder Pro programming and runtime reconfiguration
INTR	Interrupt output	Open-drain status indicator for loss-of-lock and loss-of-signal events; configurable polarity

Key Features

Feature	Design Value
MultiSynth™ synthesis engine	Enables independent, any-frequency generation on all four outputs with true zero-ppm accuracy and 1 ppb resolution
PCIe Gen 1–4 compliance	Meets Common Clock (Gen 1/2/3/4) and Gen 3 Separate Reference No Spread (SRNS) jitter specs without external filtering
Independent per-output voltage control	Each of four output banks supports 1.5 V, 1.8 V, 2.5 V, or 3.3 V logic levels-enabling direct interface to mixed-voltage FPGAs and ASICs
Glitchless frequency tuning	1 ppm step size with pin-controlled or I²C-initiated increment/decrement; no output interruption during adjustment
Programmable spread spectrum	Configurable on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, 5–350 MHz carrier-reducing EMI in dense PCB layouts
External feedback mode	Supports zero-delay operation for clock distribution networks where output-to-input phase alignment is critical

Applications

Ethernet Switch/Router Timing	PCIe Gen 3/4 Clocking
Use Scenario: High-density 1 GbE/10 GbE line cards requiring multiple synchronized clocks for MAC, PHY, and packet processor subsystems. IC Role / Device Role / Timing Role: Quad clock generator providing four independent, low-jitter clocks (e.g., 125 MHz, 156.25 MHz, 250 MHz, 312.5 MHz) with matched skew and deterministic phase relationships. Use Value: Eliminates four discrete oscillators and associated layout complexity; reduces board area by >60% versus discrete solution while meeting IEEE 802.3 jitter limits.	Use Scenario: Server motherboard or accelerator card implementing PCIe Gen 3 or Gen 4 root complex with strict common clock jitter requirements. IC Role / Device Role / Timing Role: Primary clock source delivering 100 MHz differential HCSL clocks compliant with PCIe Base Spec 3.0/4.0 SRNS and common clock modes. Use Value: Achieves 0.11–0.45 ps RMS jitter in Gen 3 SRNS mode-below PCIe spec limit-without external jitter cleaners or filters.
FPGA & Processor Clocking	Broadcast Video/Audio Timing
Use Scenario: Multi-FPGA systems (e.g., AI inference accelerators) needing precisely phased clocks for DDR interfaces, transceivers, and logic fabric. IC Role / Device Role / Timing Role: Configurable clock synthesizer generating 300 MHz LVDS for memory interfaces, 250 MHz LVPECL for SerDes, and 100 MHz CMOS for control logic-all from one device. Use Value: Enables sub-20 ps inter-output skew and programmable phase offsets (±45 ns) for timing closure across heterogeneous FPGA domains.	Use Scenario: SMPTE ST 2110/IP media gateway requiring genlock-capable, low-phase-noise clocks for video frame synchronization and audio sample rate conversion. IC Role / Device Role / Timing Role: Any-frequency generator producing 27 MHz, 74.25 MHz, 148.5 MHz, and 297 MHz outputs aligned to external video reference (e.g., tri-level sync). Use Value: Supports seamless switching between broadcast standards (NTSC/PAL/1080p/4K) via I²C reprogramming-no hardware change required.

Ethernet Switch/Router Timing

PCIe Gen 3/4 Clocking

Use Scenario: High-density 1 GbE/10 GbE line cards requiring multiple synchronized clocks for MAC, PHY, and packet processor subsystems.

IC Role / Device Role / Timing Role: Quad clock generator providing four independent, low-jitter clocks (e.g., 125 MHz, 156.25 MHz, 250 MHz, 312.5 MHz) with matched skew and deterministic phase relationships.

Use Value: Eliminates four discrete oscillators and associated layout complexity; reduces board area by >60% versus discrete solution while meeting IEEE 802.3 jitter limits.

Use Scenario: Server motherboard or accelerator card implementing PCIe Gen 3 or Gen 4 root complex with strict common clock jitter requirements.

IC Role / Device Role / Timing Role: Primary clock source delivering 100 MHz differential HCSL clocks compliant with PCIe Base Spec 3.0/4.0 SRNS and common clock modes.

Use Value: Achieves 0.11–0.45 ps RMS jitter in Gen 3 SRNS mode-below PCIe spec limit-without external jitter cleaners or filters.

FPGA & Processor Clocking

Broadcast Video/Audio Timing

Use Scenario: Multi-FPGA systems (e.g., AI inference accelerators) needing precisely phased clocks for DDR interfaces, transceivers, and logic fabric.

IC Role / Device Role / Timing Role: Configurable clock synthesizer generating 300 MHz LVDS for memory interfaces, 250 MHz LVPECL for SerDes, and 100 MHz CMOS for control logic-all from one device.

Use Value: Enables sub-20 ps inter-output skew and programmable phase offsets (±45 ns) for timing closure across heterogeneous FPGA domains.

Use Scenario: SMPTE ST 2110/IP media gateway requiring genlock-capable, low-phase-noise clocks for video frame synchronization and audio sample rate conversion.

IC Role / Device Role / Timing Role: Any-frequency generator producing 27 MHz, 74.25 MHz, 148.5 MHz, and 297 MHz outputs aligned to external video reference (e.g., tri-level sync).

Use Value: Supports seamless switching between broadcast standards (NTSC/PAL/1080p/4K) via I²C reprogramming-no hardware change required.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B04075-GM	Same silicon die and pinout; differs only in factory-programmed NVM content (different default frequency configuration)	Identical use cases; requires no design change but may need ClockBuilder Pro reconfiguration for target frequencies	Select when pre-programmed startup frequencies match system boot requirements without I²C initialization
ICS853S01AGI-01LFT	Fixed-frequency, non-programmable quad LVDS generator; 0.9 ps RMS jitter; no I²C interface or MultiSynth capability	Limited to static clock trees; cannot support dynamic frequency changes or mixed-format outputs	Choose for cost-sensitive, fixed-clock applications where flexibility is unnecessary and lower BOM count is prioritized

Compared with SI5338Q-B04075-GMR, Si5338A-B04075-GM offers identical hardware functionality but different factory defaults, while ICS853S01AGI-01LFT trades programmability for lower unit cost and simpler integration in static timing architectures.

Availability

SI5338Q-B04075-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 3/4 clocking, and FPGA/processor clocking applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338Q-B04075-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and industrial markets.

The Si5338 product line delivers high-performance, software-programmable clock generation for systems demanding multi-frequency, low-jitter timing with minimal footprint-targeting data center, telecom, and broadcast equipment.

FAQ

What is the primary function of the SI5338Q-B04075-GMR in a timing architecture?

The SI5338Q-B04075-GMR serves as an I²C-programmable quad clock generator that synthesizes four independent, low-jitter output clocks from a single reference input. Its MultiSynth™ technology enables any-frequency generation (0.16–710 MHz) with zero-ppm accuracy, making it ideal for replacing multiple discrete oscillators in systems like PCIe root complexes and Ethernet switches. SI5338Q-B04075-GMR eliminates the need for custom crystal selection and reduces board space while maintaining strict jitter compliance.

Does the SI5338Q-B04075-GMR support PCIe Gen 4 common clock requirements?

Yes, the SI5338Q-B04075-GMR meets PCIe Gen 4 common clock jitter specifications with 0.15–0.45 ps RMS (10 kHz–50 MHz) when configured per Skyworks' recommended settings-including PLL bandwidth of 2–4 MHz and CDR = 10 MHz. This performance is validated using the Skyworks PCIe Clock Jitter Tool and aligns with PCI-Express Base Specification 4.0 rev. 0.5. SI5338Q-B04075-GMR achieves this without external jitter-cleaning circuitry.

Can the SI5338Q-B04075-GMR generate different output formats simultaneously?

Yes, the SI5338Q-B04075-GMR supports simultaneous mixed-format outputs: for example, LVDS on CLK0A/B, HCSL on CLK1A/B, CMOS on CLK2A/B, and SSTL on CLK3A/B-all independently configured. Each output bank has its own VDDO supply rail (1.5/1.8/2.5/3.3 V), allowing direct interface to diverse logic families without level shifters. SI5338Q-B04075-GMR's per-output format and voltage control enables true heterogeneous clock distribution.

How is the SI5338Q-B04075-GMR programmed and configured?

The SI5338Q-B04075-GMR is programmed via its I²C/SMBus-compatible serial interface using Skyworks' ClockBuilder Pro software, which provides GUI-based frequency planning, register configuration, and EEPROM programming. Configuration can be stored in on-chip OTP NVM for autonomous startup or loaded dynamically at runtime. SI5338Q-B04075-GMR also supports pin-controlled frequency increment/decrement and phase adjustment without host intervention.

What thermal and power characteristics define the SI5338Q-B04075-GMR's suitability for high-density designs?

The SI5338Q-B04075-GMR draws 45 mA typical core current at full operation (100 MHz on all outputs) and features a 4 × 4 mm QFN package with θJA = 37 °C/W, enabling reliable operation in thermally constrained environments. Its integrated PSRR optimization and independent output supply rails minimize noise coupling. SI5338Q-B04075-GMR maintains full specification compliance from –40 °C to +85 °C ambient, supporting industrial-grade deployment without forced airflow.

SI5338Q-B04075-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338Q-B04075-GMR FAQ

1.How can I place an order for SI5338Q-B04075-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338Q-B04075-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338Q-B04075-GMR reliable?

The price and inventory of SI5338Q-B04075-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338Q-B04075-GMR is usually 5 days.

3.What payment methods are accepted for SI5338Q-B04075-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338Q-B04075-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338Q-B04075-GMR?

SI5338Q-B04075-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338Q-B04075-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338Q-B04075-GMR?

For technical support, including SI5338Q-B04075-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338Q-B04075-GMR requirements.

6.How does Aetrix verify that SI5338Q-B04075-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338Q-B04075-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338Q-B04075-GMR meets industry standards.

7.What is the process for return or replacement of SI5338Q-B04075-GMR?

All SI5338Q-B04075-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338Q-B04075-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338Q-B04075-GMR part is unused and in its original packaging.

Return procedure for SI5338Q-B04075-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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