Skyworks Solutions Inc. SI5338Q-B04079-GM
- Part No.:
- SI5338Q-B04079-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338Q-B04079-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338Q-B04079-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and support for input frequencies up to 710 MHz. It replaces multiple crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA clock trees.
For engineers reviewing the SI5338Q-B04079-GM datasheet, SI5338Q-B04079-GM pinout, SI5338Q-B04079-GM application, or SI5338Q-B04079-GM equivalent, key selection criteria include its MultiSynth™ fractional-N synthesis architecture, independent per-output voltage (1.5/1.8/2.5/3.3 V), ±20 ps phase step resolution, and 24-pin 4×4 mm QFN package with validated PCIe Gen 4 jitter performance.
Technical Context
The SI5338Q-B04079-GM implements a two-stage PLL architecture: a high-stability integer-N Phase-Locked Loop (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesis blocks (Stage 2) generating each output. This enables true zero-ppm frequency accuracy across all four outputs simultaneously.
Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with programmable slew rate, amplitude, and termination; independent phase offset (±45 ns), frequency increment/decrement (1 ppm steps), and spread-spectrum control (0.5–5.0% down-spread, 33–63 kHz modulation) are implemented via I²C or hardware pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock TJ spec < 33.6 ps pk-pk |
| Output Count & Type | 4 differential outputs (CLK0A/B–CLK3A/B); supports up to 8 single-ended or mixed configurations |
| Frequency Range | 0.16–710 MHz per output; integer/fractional synthesis with 1 ppb resolution |
| Input Flexibility | 6 inputs: crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Supply Voltages | Core: 1.8/2.5/3.3 V; independent output buffers: 1.5/1.8/2.5/3.3 V per driver |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad |
| Operating Temp | –40 °C to +85 °C ambient; qualified for industrial and telecom line card deployment |
Pinout & Package
SI5338Q-B04079-GM uses a 24-pin 4×4 mm QFN package with exposed thermal pad (pin 24). Pin functions are defined per Skyworks Rev. 1.6 datasheet, with dedicated differential input pairs (IN1/IN2, IN5/IN6), single-ended inputs (IN3, IN4), four differential output pairs (CLK0A/B–CLK3A/B), three output supply rails (VDDO0–VDDO3), core supply (VDD), I²C interface (SCL/SDA), interrupt (INTR), and reserved ground (RSVD_GND).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1 / IN2 | Differential reference input pair | Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enabled |
| CLK0A / CLK0B | Differential output pair 0 | Configurable format (LVPECL/LVDS/HCSL); independent voltage (VDDO0), phase, and enable |
| VDDO0 | Output buffer supply for CLK0A/B | 1.5/1.8/2.5/3.3 V selectable; decoupling required per layout guidelines |
| SCL / SDA | I²C serial interface | Standard-mode (100 kHz) and fast-mode (400 kHz) compatible; SMBus alert supported |
| INTR | Interrupt output | Open-drain status signal indicating loss-of-lock, loss-of-signal, or configuration error |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Four independent fractional-N synthesizers enabling any-frequency generation with 0 ppm error on all outputs |
| PCIe Gen 4 compliance | Validated 0.15–0.45 ps RMS jitter in common clock mode per PCIe Base Spec 4.0 rev. 0.5 |
| Independent output control | Per-output voltage, format, phase offset (±45 ns), frequency step (1 ppm), and spread-spectrum parameters |
| Low-power operation | 45 mA typical core current at 100 MHz on all outputs; <12 mA in buffer-only (PLL bypass) mode |
| Flexible reference inputs | Supports crystal, CMOS, SSTL, HSTL, and differential clocks - eliminates need for external level translators |
Applications
| PCIe Gen 4 Root Complex Timing | Ethernet Switch Clock Tree |
|---|---|
|
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 endpoints and upstream ports in a server motherboard. IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter, phase-aligned clocks meeting PCIe Gen 4 common clock jitter mask. Use Value: Eliminates four discrete oscillators; enables dynamic frequency scaling and spread-spectrum control to reduce EMI without compromising link stability. |
Use Scenario: Generating 156.25 MHz SerDes clocks and 25 MHz management clocks for a 32-port 10GbE switch ASIC and PHYs. IC Role / Device Role / Timing Role: Programmable frequency translator converting a 25 MHz crystal into multiple precision Ethernet rates (125 MHz, 156.25 MHz, 312.5 MHz). Use Value: Single-chip solution reduces BOM count and PCB area; independent output voltage control matches ASIC and PHY I/O voltage requirements. |
| FPGA/ASIC Clock Distribution | Broadcast Video Synchronization |
|
Use Scenario: Supplying 300 MHz transceiver reference, 100 MHz logic clock, and 50 MHz debug clock to a Xilinx Versal ACAP with mixed-voltage I/O banks. IC Role / Device Role / Timing Role: Configurable quad clock source with per-output voltage (1.8 V, 2.5 V, 3.3 V) and format (LVDS, HCSL, CMOS) matching heterogeneous FPGA interfaces. Use Value: Avoids level-shifting buffers and discrete clock ICs; phase adjustment ensures setup/hold margin optimization across clock domains. |
Use Scenario: Delivering SMPTE ST 2059-2 compliant 27 MHz, 74.25 MHz, and 148.5 MHz video reference clocks to camera heads, frame synchronizers, and encoder boards in 4K/8K OB vans. IC Role / Device Role / Timing Role: High-stability, low-phase-noise clock generator supporting broadcast-grade jitter specs (<0.5 ps RMS) and seamless format switching. Use Value: Replaces legacy crystal-based solutions with field-upgradable timing; independent spread-spectrum control suppresses harmonics in RF-sensitive environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D05180-GM | Higher integration: 8 outputs, integrated EEPROM, enhanced jitter (0.35 ps RMS), Gen 5 PCIe ready | Targets next-gen systems requiring >4 outputs or factory pre-programming; larger 32-QFN package | Select when future-proofing for PCIe Gen 5 or needing more outputs; requires layout revision |
| ICS8430I-01T | Fixed-frequency, non-programmable quad LVDS generator; 1.2 ps RMS jitter; no I²C interface | Used in cost-sensitive, static-clock applications where frequency flexibility is unnecessary | Select only for fixed-rate designs with no requirement for reconfiguration or multi-standard support |
Compared with Si5332A-D05180-GM, SI5338Q-B04079-GM offers lower cost and smaller footprint for Gen 4-compliant 4-output needs; compared with ICS8430I-01T, it provides full field programmability and superior jitter performance at the expense of higher design complexity.
Availability
SI5338Q-B04079-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server platforms, 10GbE switch designs, and FPGA-based embedded vision systems requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for SI5338Q-B04079-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 40 years of RF and clocking expertise.
The Si5338 family was designed for high-performance, multi-protocol serial interface timing - specifically targeting PCIe, Ethernet, Fibre Channel, and broadcast video systems requiring flexible, low-jitter clock synthesis in compact form factors.
FAQ
What is the primary function of the SI5338Q-B04079-GM in a PCIe Gen 4 system?
The SI5338Q-B04079-GM serves as a quad-output clock generator delivering four synchronized, low-jitter reference clocks (typically 100 MHz) to PCIe Gen 4 root complex and endpoint devices. Its 0.15–0.45 ps RMS jitter performance meets PCIe Base Specification 4.0 common clock requirements, and its independent output control allows per-port spread-spectrum tuning to reduce EMI without violating jitter masks. The SI5338Q-B04079-GM replaces multiple discrete oscillators while maintaining phase alignment across lanes.
Does the SI5338Q-B04079-GM support both differential and single-ended output formats?
Yes, the SI5338Q-B04079-GM supports differential outputs (LVPECL, LVDS, HCSL, CML) and single-ended outputs (CMOS, SSTL, HSTL) across its four output drivers. Each output can be independently configured for format, voltage (1.5/1.8/2.5/3.3 V), and termination. For example, CLK0A/B may be set to LVDS at 1.8 V while CLK1A/B operates as CMOS at 3.3 V - all simultaneously. The SI5338Q-B04079-GM datasheet specifies drive strength, rise/fall time, and voltage swing limits for each combination.
How is the SI5338Q-B04079-GM programmed, and what tools are required?
The SI5338Q-B04079-GM is programmed via its I²C/SMBus-compatible serial interface using Skyworks' ClockBuilder Pro software, which generates configuration files and register maps based on user-defined frequency, format, and feature requirements. Programming can be performed in-system during manufacturing or in the field. The SI5338Q-B04079-GM also supports pin-strapped default configurations and hardware-controlled frequency/phase adjustments. No external programming hardware is needed beyond standard I²C access.
What is the maximum input frequency the SI5338Q-B04079-GM accepts, and what interface types are supported?
The SI5338Q-B04079-GM accepts input frequencies up to 710 MHz on its differential input pins (IN1/IN2, IN5/IN6), 350 MHz on SSTL/HSTL inputs (IN3/IN4), and 200 MHz on CMOS inputs. Supported interfaces include: 8–30 MHz fundamental-mode crystals; single-ended CMOS (5–200 MHz); SSTL/HSTL (5–350 MHz); and AC-coupled differential (5–710 MHz). All inputs are internally terminated and level-shifted, eliminating external biasing components. The SI5338Q-B04079-GM automatically detects and conditions each input type.
Is the SI5338Q-B04079-GM suitable for industrial temperature applications?
Yes, the SI5338Q-B04079-GM is rated for operation from –40 °C to +85 °C ambient temperature and is qualified for industrial applications. Its specifications - including phase jitter (0.7 ps RMS), supply current (45 mA typ), and output voltage accuracy - are guaranteed across this full range. Thermal resistance (θJA = 37 °C/W) and junction temperature limits (150 °C) ensure reliable operation in enclosed, convection-cooled environments typical of industrial controllers and telecom line cards. The SI5338Q-B04079-GM has been deployed in base station radios and industrial Ethernet switches operating continuously at 85 °C.
SI5338Q-B04079-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338Q-B04079-GM FAQ
1.How can I place an order for SI5338Q-B04079-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338Q-B04079-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338Q-B04079-GM reliable?
The price and inventory of SI5338Q-B04079-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338Q-B04079-GM is usually 5 days.
3.What payment methods are accepted for SI5338Q-B04079-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338Q-B04079-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338Q-B04079-GM?
SI5338Q-B04079-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338Q-B04079-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338Q-B04079-GM?
For technical support, including SI5338Q-B04079-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338Q-B04079-GM requirements.
6.How does Aetrix verify that SI5338Q-B04079-GM is sourced from the original manufacturer or authorized distributors?
All SI5338Q-B04079-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338Q-B04079-GM meets industry standards.
7.What is the process for return or replacement of SI5338Q-B04079-GM?
All SI5338Q-B04079-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338Q-B04079-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338Q-B04079-GM part is unused and in its original packaging.
Return procedure for SI5338Q-B04079-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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