Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338Q-B04079-GMR

Name: SI5338Q-B04079-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338Q-B04079-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338Q-B04079-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338Q-B04079-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,882

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338Q-B04079-GMR from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338Q-B04079-GMR datasheet, SI5338Q-B04079-GMR pinout, SI5338Q-B04079-GMR application, or SI5338Q-B04079-GMR equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ any-frequency synthesis (0.16–710 MHz), spread-spectrum control (0.5–5.0% at 33–63 kHz), and loss-of-lock/loss-of-signal alarm support.

Technical Context

The SI5338Q-B04079-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesis blocks, each driving a configurable output buffer. Its input stage accepts differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or crystal (8–30 MHz) references.

Each output supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent voltage rails (VDDO0–VDDO3), programmable phase offset (±45 ns), glitchless frequency increment/decrement (1 ppm steps), and configurable spread spectrum (5–350 MHz, 0.5–5.0%, 33–63 kHz). The device operates across –40 to +85 °C with 45 mA typical core current.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 4 common clock jitter requirement (≤0.45 ps RMS) under specified test conditions
Output Frequency Range	0.16–710 MHz - supports PCIe 100 MHz HCSL, 156.25 MHz Ethernet, 125 MHz GbE, and 250 MHz FPGA clocks
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - enables flexible system clock tree design
Output Format Flexibility	LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL - allows direct interface to processors, FPGAs, SerDes, and memory controllers without level-shifting
Supply Voltages	VDD = 1.8/2.5/3.3 V ±10%; VDDOx = 1.4–3.63 V - supports mixed-voltage SoC/FPGA platforms
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch - space-efficient for dense PCB layouts with thermal pad for heat dissipation
Temperature Range	–40 to +85 °C - qualified for industrial and telecom line card environments

Pinout & Package

SI5338Q-B04079-GMR is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept AC-coupled LVPECL/LVDS/CML reference clocks up to 710 MHz; require external 100 Ω termination
IN3, IN4	Single-ended CMOS inputs	Support DC-coupled 5–200 MHz clocks; VIH ≥ 0.7×VDD, VIL ≤ 0.3×VDD
CLK0A–CLK3B	Differential output pairs (4 channels)	Configurable as LVPECL/LVDS/HCSL/CML; each pair shares VDDOx rail and format setting
VDDO0–VDDO3	Independent output buffer supplies	Enable per-output voltage selection (1.5/1.8/2.5/3.3 V) for mixed-interface systems
SCL, SDA	I²C/SMBus interface	Standard 100/400 kHz operation; supports ClockBuilder Pro programming and runtime reconfiguration
INTR	Interrupt output	Open-drain status signal indicating loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ any-frequency synthesis	Four independent outputs with true zero-ppm accuracy across 0.16–710 MHz, eliminating need for multiple crystals
PCIe Gen 4 Common Clock compliance	0.15–0.45 ps RMS jitter at 100 MHz HCSL output satisfies PCIe Base Spec 4.0 rev 0.5 timing budget
Independent output voltage per driver	VDDO0–VDDO3 pins allow simultaneous 1.8 V LVDS and 3.3 V CMOS outputs on same device
Glitchless frequency adjustment	1 ppm step size with pin-controlled or I²C-initiated increment/decrement, enabling dynamic clock scaling
Programmable spread spectrum	Configurable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) per output to reduce EMI peaks
Loss-of-lock and loss-of-signal alarms	INTR pin asserts open-drain low on detection, enabling real-time system health monitoring without polling

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized 100 MHz HCSL clocks to PCIe Gen 4 switch fabric and attached endpoints in data center switches. IC Role / Device Role / Timing Role: Quad-output clock generator delivering PCIe-compliant common clock with <0.45 ps RMS jitter and loss-of-lock monitoring. Use Value: Eliminates four discrete oscillators while meeting PCIe Gen 4 jitter mask and enabling real-time fault detection via INTR pin.	Use Scenario: Generating 125 MHz LVDS and 156.25 MHz LVPECL clocks for 1/10 GbE PHYs and packet processors in enterprise routers. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing precise Ethernet reference clocks with independent voltage rails and format control. Use Value: Supports mixed-voltage PHY interfaces (1.8 V LVDS + 2.5 V LVPECL) from a single IC, reducing BOM count and layout area.
FPGA-Based Video Processing	Telecom Line Card Synchronization
Use Scenario: Supplying 250 MHz LVDS pixel clock and 148.5 MHz LVPECL video timing reference to FPGA-based broadcast encoders. IC Role / Device Role / Timing Role: Low-jitter quad generator with independent phase adjustment (±45 ns, <20 ps steps) for skew compensation across parallel video lanes. Use Value: Enables deterministic inter-lane alignment without external delay lines, simplifying high-resolution video timing design.	Use Scenario: Distributing synchronized 19.44 MHz OC-12 and 155.52 MHz SONET/SDH clocks across multi-slot telecom line cards. IC Role / Device Role / Timing Role: High-stability clock translator accepting 10 MHz TCXO input and generating telecom-grade outputs with 0.7 ps RMS jitter. Use Value: Replaces legacy clock trees with single-chip solution meeting ITU-T G.823/G.8262 jitter requirements for synchronous optical networks.

PCIe Gen 4 Switch Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized 100 MHz HCSL clocks to PCIe Gen 4 switch fabric and attached endpoints in data center switches.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering PCIe-compliant common clock with <0.45 ps RMS jitter and loss-of-lock monitoring.

Use Value: Eliminates four discrete oscillators while meeting PCIe Gen 4 jitter mask and enabling real-time fault detection via INTR pin.

Use Scenario: Generating 125 MHz LVDS and 156.25 MHz LVPECL clocks for 1/10 GbE PHYs and packet processors in enterprise routers.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing precise Ethernet reference clocks with independent voltage rails and format control.

Use Value: Supports mixed-voltage PHY interfaces (1.8 V LVDS + 2.5 V LVPECL) from a single IC, reducing BOM count and layout area.

FPGA-Based Video Processing

Telecom Line Card Synchronization

Use Scenario: Supplying 250 MHz LVDS pixel clock and 148.5 MHz LVPECL video timing reference to FPGA-based broadcast encoders.

IC Role / Device Role / Timing Role: Low-jitter quad generator with independent phase adjustment (±45 ns, <20 ps steps) for skew compensation across parallel video lanes.

Use Value: Enables deterministic inter-lane alignment without external delay lines, simplifying high-resolution video timing design.

Use Scenario: Distributing synchronized 19.44 MHz OC-12 and 155.52 MHz SONET/SDH clocks across multi-slot telecom line cards.

IC Role / Device Role / Timing Role: High-stability clock translator accepting 10 MHz TCXO input and generating telecom-grade outputs with 0.7 ps RMS jitter.

Use Value: Replaces legacy clock trees with single-chip solution meeting ITU-T G.823/G.8262 jitter requirements for synchronous optical networks.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06107-GM	Higher integration: includes integrated crystal, lower jitter (0.35 ps RMS), supports up to 12 outputs via fanout mode	Targeted at new designs requiring ultra-low jitter and reduced external components; not drop-in compatible due to different pinout and register map	Select when PCIe Gen 5 readiness, integrated crystal, or >4 outputs are required; requires full redesign and ClockBuilder Pro reconfiguration
ICS8430I-01T	Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; 3.3 V only; no spread spectrum or phase adjustment	Suitable for cost-sensitive, static-clock applications where flexibility is unnecessary and jitter margin is relaxed	Choose for legacy systems with fixed 100/125/156.25 MHz clocks and no need for runtime reconfiguration or EMI reduction

Compared with Si5332A-D06107-GM and ICS8430I-01T, SI5338Q-B04079-GMR offers balanced programmability, PCIe Gen 4 compliance, and industrial temperature support in a proven 24-QFN footprint-making it optimal for mid-cycle upgrades and mixed-signal timing consolidation where flexibility and qualification stability are critical.

Availability

SI5338Q-B04079-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch clocking, FPGA-based video processing, and telecom line card synchronization requiring stable component supply and long-term industrial qualification.

Supply support for SI5338Q-B04079-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed for high-performance, software-configurable clock generation in data center, networking, and communications equipment-emphasizing low jitter, multi-format output flexibility, and PCIe compliance.

FAQ

What is the maximum output frequency supported by SI5338Q-B04079-GMR in LVPECL format?

The SI5338Q-B04079-GMR supports LVPECL outputs up to 710 MHz, as confirmed in Table 6 of the datasheet. This capability enables direct clocking of high-speed SerDes lanes in PCIe Gen 4 and 10 GbE applications. Operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6), and requires proper termination with external 100 Ω differential loads per LVPECL specification.

Does SI5338Q-B04079-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338Q-B04079-GMR is compliant with PCIe Gen 4 SRNS requirements, achieving 0.11–0.32 ps RMS jitter under specified test conditions (PLL BW 2–5 MHz, CDR = 10 MHz). This compliance is explicitly stated in the Features section and verified in Table 12's PCIe Gen 3 SRNS row, which applies to Gen 4 per Skyworks' documentation hierarchy and PCIe Base Spec 4.0 alignment.

Can SI5338Q-B04079-GMR generate different output voltages on its four channels simultaneously?

Yes, SI5338Q-B04079-GMR supports independent output supply rails via VDDO0, VDDO1, VDDO2, and VDDO3 pins, allowing concurrent 1.8 V LVDS, 2.5 V HCSL, 3.3 V CMOS, and 1.5 V SSTL outputs. Each VDDOx pin powers its associated CLKxA/CLKxB pair, and voltage selection is hardware-defined-not register-configured-ensuring robust mixed-voltage timing in heterogeneous SoC/FPGA systems.

How is the SI5338Q-B04079-GMR programmed, and is external non-volatile memory required?

SI5338Q-B04079-GMR is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software, which generates configuration files loaded at power-up. The device contains on-chip one-time-programmable (OTP) NVM that stores the default configuration; no external memory is required for boot-time initialization. Factory-programmed variants like SI5338Q-B04079-GMR ship with preloaded settings optimized for common use cases.

What thermal performance can be expected from SI5338Q-B04079-GMR in a standard 4-layer PCB layout?

SI5338Q-B04079-GMR has a junction-to-ambient thermal resistance (θJA) of 37 °C/W under still-air conditions, as specified in Table 4. With its exposed thermal pad, typical board-level thermal performance achieves ≤55 °C junction rise at 45 mA core current (100 MHz all outputs, 25 MHz refclk). Maintaining ≥4 cm² copper pour connected to the thermal pad and ≥2 vias (0.3 mm diameter) significantly improves heat dissipation in industrial ambient conditions.

SI5338Q-B04079-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338Q-B04079-GMR FAQ

1.How can I place an order for SI5338Q-B04079-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338Q-B04079-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338Q-B04079-GMR reliable?

The price and inventory of SI5338Q-B04079-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338Q-B04079-GMR is usually 5 days.

3.What payment methods are accepted for SI5338Q-B04079-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338Q-B04079-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338Q-B04079-GMR?

SI5338Q-B04079-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338Q-B04079-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338Q-B04079-GMR?

For technical support, including SI5338Q-B04079-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338Q-B04079-GMR requirements.

6.How does Aetrix verify that SI5338Q-B04079-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338Q-B04079-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338Q-B04079-GMR meets industry standards.

7.What is the process for return or replacement of SI5338Q-B04079-GMR?

All SI5338Q-B04079-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338Q-B04079-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338Q-B04079-GMR part is unused and in its original packaging.

Return procedure for SI5338Q-B04079-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…