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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338Q-B04172-GMR

Name: SI5338Q-B04172-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338Q-B04172-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338Q-B04172-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338Q-B04172-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338Q-B04172-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and MultiSynth™ frequency synthesis supporting 0.16–710 MHz output ranges across LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338Q-B04172-GMR datasheet, SI5338Q-B04172-GMR pinout, SI5338Q-B04172-GMR application, or SI5338Q-B04172-GMR equivalent, key selection considerations include its 24-QFN package, independent per-output voltage (1.5/1.8/2.5/3.3 V), ±20 ps phase step resolution, 1 ppm frequency increment/decrement capability, and support for external crystal (8–30 MHz) or wide-band differential inputs (5–710 MHz).

Technical Context

The SI5338Q-B04172-GMR implements a two-stage PLL architecture: a high-stability reference PLL (Stage 1) locks to one of six input sources, followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output with integer or fractional division. Each output driver supports format and voltage selection, spread-spectrum modulation (0.5–5.0% at 33–63 kHz), and glitchless frequency/phase adjustment via pin control or I²C.

It operates from a single 1.8/2.5/3.3 V core supply with 45 mA typical current draw, integrates OTP NVM for factory or field programming, and delivers <100 ps output-to-output skew under matched divider conditions. Loss-of-lock and loss-of-signal alarms are provided on the INTR pin, and external feedback enables zero-delay mode.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - Meets PCIe Gen 3/4 common clock and SRNS requirements; measured 12 kHz–20 MHz band with differential LVDS/HCSL outputs.
Output Frequency Range	0.16–710 MHz - Supports LVPECL/LVDS (≤710 MHz), HCSL (≤250 MHz), CMOS (≤200 MHz), SSTL/HSTL (≤350 MHz); two >350 MHz frequencies simultaneously allowed.
Input Reference Support	8–30 MHz crystal, or 5–710 MHz differential/CMOS/SSTL/HSTL - Enables flexible sourcing including PCIe REFCLK, Ethernet PHY clocks, or FPGA clocks.
Supply Voltages	VDD = 1.8/2.5/3.3 V ±10%; VDDOx = 1.5/1.8/2.5/3.3 V - Independent output buffer supplies allow mixed-voltage system interfacing without level shifters.
Frequency Resolution	1 ppb - Achieved via fractional-N MultiSynth™; enables exact synthesis of non-integer-related frequencies (e.g., 156.25 MHz, 122.88 MHz, 100.0125 MHz).
Phase Adjustment	±45 ns range in <20 ps steps - Enables fine-grained deskew between outputs for SerDes lane alignment or DDR timing margin optimization.
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch - Surface-mount footprint compatible with high-density PCB layouts; exposed thermal pad improves thermal performance.

Pinout & Package

SI5338Q-B04172-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow the standard Si5338 top-view layout.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential input pair #1	Accepts AC-coupled 5–710 MHz differential clock; internal 100 Ω termination enabled when used as primary reference.
IN3, IN4	Single-ended input pair	Supports CMOS/SSTL/HSTL inputs (5–350 MHz); IN3 is active low reset if pulled low during power-up.
IN5, IN6	Differential input pair #2	Secondary differential reference path; identical electrical specs to IN1/IN2.
CLK0A, CLK0B – CLK3A, CLK3B	Differential output pairs	Four fully independent outputs; each configurable for LVPECL/LVDS/HCSL/CML with dedicated VDDOx supply.
VDDO0–VDDO3	Output buffer supply pins	Enable per-output voltage setting (1.5/1.8/2.5/3.3 V); decoupling required per output domain.
SCL, SDA	I²C interface	Standard SMBus-compatible 100/400 kHz interface; supports ClockBuilder Pro configuration and runtime reprogramming.
INTR	Interrupt output	Open-drain status pin asserting on loss-of-lock, loss-of-signal, or NVM checksum error.
VDD	Core supply	Single 1.8/2.5/3.3 V supply powering PLL, logic, and memory; PSRR optimized for noisy digital environments.
GND, RSVD_GND	Ground connections	Multiple GND pins and reserved ground pad ensure low-impedance return paths and minimize jitter coupling.

Key Features

Feature	Design Value
MultiSynth™ synthesis engine	Enables true zero-ppm accuracy on all four outputs with independent fractional-N dividers - eliminates need for multiple crystals or discrete synthesizers.
PCIe Gen 1–4 & SRNS compliance	Validated 0.11–0.45 ps RMS jitter in Gen 3 SRNS and Gen 4 common clock modes - meets Intel and PCI-SIG timing specifications without external cleanup.
Independent output voltage per channel	Each of four outputs powered by separate VDDOx rail (1.5/1.8/2.5/3.3 V) - simplifies mixed-voltage SoC/FPGA clock tree design and avoids level-shifter components.
Glitchless frequency tuning	1 ppm step size with pin-controlled increment/decrement - enables real-time dynamic frequency scaling in test equipment or adaptive systems without clock interruption.
Programmable spread spectrum	Configurable 0.5–5.0% down-spread at 33–63 kHz on any output - reduces EMI peak emissions in noise-sensitive applications like broadcast video or medical imaging.
External feedback mode	Supports zero-delay operation by feeding back a clock output to an input pin - maintains precise phase alignment in daisy-chained clock distribution networks.

Applications

PCIe Gen 4 Switch Timing	Ethernet 10GbE Line Card
Use Scenario: Providing synchronized reference clocks to a 32-lane PCIe Gen 4 switch ASIC and attached NVMe SSDs in a data center server blade. IC Role / Device Role / Timing Role: Quad-output clock generator delivering 100 MHz common clock and 100.0125 MHz SRNS reference with sub-0.32 ps RMS jitter to meet PCIe Base Spec 4.0. Use Value: Eliminates four discrete oscillators and associated layout area; ensures deterministic inter-lane skew <100 ps for reliable 16 GT/s link training.	Use Scenario: Generating parallel clocks for 10GbE PHYs, MAC processors, and packet buffer controllers on a telecom line card. IC Role / Device Role / Timing Role: Configured with 156.25 MHz (XAUI), 125 MHz (RX/TX), and 250 MHz (DDR3 controller) outputs using LVDS and CMOS formats. Use Value: Single-device solution supports multi-protocol timing with independent voltage domains (1.8 V for PHYs, 2.5 V for DDR), reducing BOM count and power delivery complexity.
Broadcast Video Master Clock	FPGA-Based Test Equipment
Use Scenario: Serving as master timing source for SMPTE ST 2082 (12G-SDI) and ST 2110 (IP video) processing in a broadcast camera head. IC Role / Device Role / Timing Role: Produces 27 MHz, 74.25 MHz, and 148.5 MHz outputs with <10 ps cycle-cycle jitter to meet SMPTE RP 188 and ITU-R BT.656 jitter limits. Use Value: MultiSynth™ zero-ppm synthesis ensures frame-accurate genlock across multiple video streams without drift-induced artifacts.	Use Scenario: Supplying programmable clocks to high-speed ADC/DAC channels and FPGA fabric in automated test equipment. IC Role / Device Role / Timing Role: Delivers 122.88 MHz (JESD204B), 245.76 MHz (sample clock), and variable-frequency stimulus clocks with <20 ps phase step resolution for calibration sweeps. Use Value: Real-time pin-controlled frequency/phase tuning enables rapid test pattern iteration without firmware reload or I²C latency.

PCIe Gen 4 Switch Timing

Ethernet 10GbE Line Card

Use Scenario: Providing synchronized reference clocks to a 32-lane PCIe Gen 4 switch ASIC and attached NVMe SSDs in a data center server blade.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering 100 MHz common clock and 100.0125 MHz SRNS reference with sub-0.32 ps RMS jitter to meet PCIe Base Spec 4.0.

Use Value: Eliminates four discrete oscillators and associated layout area; ensures deterministic inter-lane skew <100 ps for reliable 16 GT/s link training.

Use Scenario: Generating parallel clocks for 10GbE PHYs, MAC processors, and packet buffer controllers on a telecom line card.

IC Role / Device Role / Timing Role: Configured with 156.25 MHz (XAUI), 125 MHz (RX/TX), and 250 MHz (DDR3 controller) outputs using LVDS and CMOS formats.

Use Value: Single-device solution supports multi-protocol timing with independent voltage domains (1.8 V for PHYs, 2.5 V for DDR), reducing BOM count and power delivery complexity.

Broadcast Video Master Clock

FPGA-Based Test Equipment

Use Scenario: Serving as master timing source for SMPTE ST 2082 (12G-SDI) and ST 2110 (IP video) processing in a broadcast camera head.

IC Role / Device Role / Timing Role: Produces 27 MHz, 74.25 MHz, and 148.5 MHz outputs with <10 ps cycle-cycle jitter to meet SMPTE RP 188 and ITU-R BT.656 jitter limits.

Use Value: MultiSynth™ zero-ppm synthesis ensures frame-accurate genlock across multiple video streams without drift-induced artifacts.

Use Scenario: Supplying programmable clocks to high-speed ADC/DAC channels and FPGA fabric in automated test equipment.

IC Role / Device Role / Timing Role: Delivers 122.88 MHz (JESD204B), 245.76 MHz (sample clock), and variable-frequency stimulus clocks with <20 ps phase step resolution for calibration sweeps.

Use Value: Real-time pin-controlled frequency/phase tuning enables rapid test pattern iteration without firmware reload or I²C latency.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B04172-GM	Same silicon die and pinout; differs only in factory-programmed OTP content - lacks pre-loaded configuration for PCIe Gen 4 SRNS mode.	Requires full ClockBuilder Pro configuration before first use; not suitable for drop-in replacement where factory-tuned settings are critical.	Select SI5338Q-B04172-GMR when PCIe Gen 4 SRNS compliance must be guaranteed out-of-box without engineering validation.
ICS853S02IAGLF	Fixed-frequency dual-output LVDS clock generator; no I²C interface, no frequency synthesis, no spread spectrum, max 200 MHz output.	Limited to static clock trees; cannot replace multiple crystals or support dynamic frequency changes.	Choose only for cost-sensitive, low-complexity designs requiring two fixed LVDS clocks below 200 MHz with no programmability.

Compared with Si5338A-B04172-GM, SI5338Q-B04172-GMR offers verified factory-programmed SRNS settings for immediate PCIe Gen 4 deployment; compared with ICS853S02IAGLF, it provides full programmability, wider frequency range, lower jitter, and four independent outputs - making it suitable for high-performance, multi-protocol timing consolidation.

Availability

SI5338Q-B04172-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10GbE line cards, and broadcast video master clocking requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338Q-B04172-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and industrial markets.

The Si5338 product line was designed to consolidate multi-frequency clock trees in high-speed serial interface systems, enabling reduced board space, improved jitter performance, and simplified system-level timing validation - particularly for PCIe, Ethernet, and broadcast video applications.

FAQ

What is the default factory configuration of the SI5338Q-B04172-GMR?

The SI5338Q-B04172-GMR ships with OTP memory pre-programmed for PCIe Gen 4 SRNS compliance: 100.0125 MHz output on CLK0A/B (HCSL, 1.8 V), 100 MHz on CLK1A/B (HCSL, 1.8 V), and configured PLL bandwidth and jitter filters validated per PCI-SIG requirements. This eliminates need for initial ClockBuilder Pro setup in PCIe applications.

Does the SI5338Q-B04172-GMR support spread-spectrum clocking on all four outputs simultaneously?

Yes, the SI5338Q-B04172-GMR supports independent spread-spectrum modulation on any or all four outputs. Each output can be configured for 0.5–5.0% down-spread at 33–63 kHz, with separate enable/disable control and modulation rate selection - enabling simultaneous EMI reduction across multiple high-speed interfaces.

Can the SI5338Q-B04172-GMR generate 122.88 MHz and 245.76 MHz simultaneously for JESD204B applications?

Yes, the SI5338Q-B04172-GMR can generate both 122.88 MHz and 245.76 MHz simultaneously using its MultiSynth™ engines. These frequencies fall within the 0.16–710 MHz LVDS/LVPECL range and are supported with <0.7 ps RMS jitter - meeting JESD204B subclass 1 deterministic latency and jitter requirements.

What is the maximum output frequency achievable in LVPECL format on the SI5338Q-B04172-GMR?

The SI5338Q-B04172-GMR supports LVPECL outputs up to 710 MHz, as confirmed in Table 6 of the datasheet. This applies when operating in integer synthesis mode with appropriate VDDO supply (2.5 V or 3.3 V) and proper AC-coupled 100 Ω termination - enabling direct clocking of high-speed SerDes lanes without external frequency multiplication.

Is the SI5338Q-B04172-GMR pin-compatible with other Si5338 variants such as the Si5338B or Si5338C?

Yes, all Si5338 variants - including SI5338Q-B04172-GMR, Si5338B, and Si5338C - share identical 24-QFN packaging, pinout, and electrical interface. Differences reside solely in factory-programmed OTP content and supported feature subsets (e.g., spread spectrum, output formats), not mechanical or signal-level compatibility.

SI5338Q-B04172-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338Q-B04172-GMR FAQ

1.How can I place an order for SI5338Q-B04172-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338Q-B04172-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338Q-B04172-GMR reliable?

The price and inventory of SI5338Q-B04172-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338Q-B04172-GMR is usually 5 days.

3.What payment methods are accepted for SI5338Q-B04172-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338Q-B04172-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338Q-B04172-GMR?

SI5338Q-B04172-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338Q-B04172-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338Q-B04172-GMR?

For technical support, including SI5338Q-B04172-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338Q-B04172-GMR requirements.

6.How does Aetrix verify that SI5338Q-B04172-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338Q-B04172-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338Q-B04172-GMR meets industry standards.

7.What is the process for return or replacement of SI5338Q-B04172-GMR?

All SI5338Q-B04172-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338Q-B04172-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338Q-B04172-GMR part is unused and in its original packaging.

Return procedure for SI5338Q-B04172-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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