Skyworks Solutions Inc. SI5338Q-B04428-GMR
- Part No.:
- SI5338Q-B04428-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338Q-B04428-GMR.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:3,628
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Product details
Overview
SI5338Q-B04428-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz), supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, achieves 0.7 ps RMS phase jitter (typ), and operates from 1.8/2.5/3.3 V core supply in PCIe Gen 1–4 and broadcast video timing systems.
For engineers reviewing the SI5338Q-B04428-GMR datasheet, SI5338Q-B04428-GMR pinout, SI5338Q-B04428-GMR application, or SI5338Q-B04428-GMR equivalent, this page provides verified specifications, validated pin functions, confirmed PCIe Gen 4 SRNS compliance, and real-world use cases for FPGA clocking, Ethernet switch timing, and telecom line card synchronization.
Technical Context
The SI5338Q-B04428-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers per output. Each output driver features programmable voltage (1.5–3.3 V), format selection, and sub-20 ps phase adjustment resolution.
It accepts six input references-including differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and 8–30 MHz crystals-and supports zero-delay mode via external feedback. Loss-of-lock and loss-of-signal alarms are integrated for system monitoring.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | Four independent differential or single-ended clock outputs |
| Frequency range | 0.16–710 MHz per output; supports integer/fractional synthesis |
| Phase jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 SRNS spec |
| Supply voltage | Core: 1.8/2.5/3.3 V ±10%; output buffers: 1.4–3.63 V independently configurable |
| Input flexibility | 6-pin reference interface supporting crystal (8–30 MHz), CMOS, SSTL/HSTL, and differential inputs up to 710 MHz |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad |
| Operating temp | –40 °C to +85 °C ambient; qualified for industrial and telecom applications |
Pinout & Package
SI5338Q-B04428-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad (RoHS-compliant, lead-free). Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND), and pin 12 is INTR (interrupt output).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential reference inputs | Accept AC-coupled differential clocks up to 710 MHz; require external 100 Ω termination |
| IN3, IN4 | Single-ended reference inputs | Support CMOS/SSTL/HSTL signals (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A/CLK0B – CLK3A/CLK3B | Differential clock outputs | Four pairs; each pair independently configurable for LVPECL/LVDS/HCSL/CML with selectable VDDOx |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.4–3.63 V rails per output bank; enable mixed-voltage clock distribution |
| SCL, SDA | I²C configuration interface | Standard SMBus-compatible bus (up to 400 kHz); supports write-protection and register lock |
| INTR | Interrupt output | Open-drain status flag indicating loss-of-lock or loss-of-signal; pulled up externally |
| VDD | Core supply | Single 1.8/2.5/3.3 V rail; PSRR > 60 dB across 10 kHz–100 MHz |
| GND, RSVD_GND | Ground terminals | Eight dedicated ground pins including thermal pad; minimize power/ground bounce in high-speed clocking |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Four independent fractional-N synthesizers enabling true zero-ppm accuracy on all outputs |
| PCIe Gen 4 SRNS compliance | 0.11–0.45 ps RMS jitter (10 kHz–50 MHz) under Gen 4 Common Clock and SRNS modes |
| Glitchless frequency tuning | 1 ppm step size with pin-controlled increment/decrement; update time ≤667 ns above 18 MHz |
| Programmable phase offset | ±45 ns range in <20 ps steps per output; enables precise skew control across multi-clock domains |
| Spread spectrum support | Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, 5–350 MHz range |
| Flexible reference handling | External crystal (8–30 MHz) or wideband clock inputs (5–710 MHz); automatic LOS detection with 2.6–5 µs response |
Applications
| PCIe Gen 4 Switch Timing | Ethernet Switch/Routing |
|---|---|
Use Scenario: High-speed server interconnect using PCIe Gen 4 switches requiring low-jitter, synchronized clocks across multiple lanes. IC Role / Device Role / Timing Role: Primary clock generator providing four independent 100 MHz HCSL clocks with SRNS-compliant jitter (<0.32 ps RMS). Use Value: Enables full Gen 4 link training and stable 16 GT/s operation without retiming; eliminates need for four discrete oscillators. |
Use Scenario: 10 GbE/25 GbE line cards in enterprise routers needing scalable, programmable clock trees. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer delivering 156.25 MHz (10GbE), 312.5 MHz (25GbE), and auxiliary clocks from one reference. Use Value: Reduces BOM count and PCB area vs. fixed-frequency XO solutions; supports field-upgradable data rates. |
| Broadcast Video/Audio Sync | FPGA & Processor Clocking |
Use Scenario: SMPTE ST 2082/2110 IP video transport systems requiring precise genlock and frame-rate conversion. IC Role / Device Role / Timing Role: Quad-output generator producing 27 MHz (SDI), 74.25 MHz (HD), 148.5 MHz (UHD), and 10 MHz reference from a single crystal. Use Value: Achieves sub-20 ps inter-output skew and <0.7 ps RMS jitter-critical for lip-sync and artifact-free video processing. |
Use Scenario: Heterogeneous SoC/FPGA platforms with mixed-voltage peripherals (e.g., DDR4, PCIe, USB3, MIPI). IC Role / Device Role / Timing Role: Configurable clock source supplying 100 MHz (PCIe), 200 MHz (DDR4), 400 MHz (USB3 PHY), and 27 MHz (MIPI D-PHY) simultaneously. Use Value: Eliminates timing closure issues via per-output voltage/format control and deterministic phase alignment. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D06989-GM | Higher integration: includes integrated LDOs, lower 0.35 ps RMS jitter, supports up to 12 outputs via fanout | Targeted at ultra-low-jitter 5G baseband and optical transport; requires different layout due to 32-QFN package | Choose when PCIe Gen 5 or OTN timing is required; not drop-in compatible due to pin count and register map differences |
| ICS853S01AG-01LF | Fixed-frequency, non-programmable quad LVDS buffer; no synthesis capability; 1.2 ps RMS jitter | Limited to static clock fanout; no frequency translation or spread spectrum | Select only for cost-sensitive, fixed-clock-count designs where reprogramming is unnecessary and jitter budget allows ≥1.2 ps RMS |
Compared with Si5332A-D06989-GM, SI5338Q-B04428-GMR offers broader input flexibility and simpler I²C programming but higher jitter; versus ICS853S01AG-01LF, it enables dynamic frequency adaptation and multi-standard compliance at the cost of configuration overhead.
Availability
SI5338Q-B04428-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10/25 GbE routing, and broadcast video synchronization requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for SI5338Q-B04428-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5338 family was designed for high-performance, software-defined clock generation in infrastructure equipment-enabling consolidation of multiple oscillators into a single programmable device with PCIe, Ethernet, and broadcast timing compliance.
FAQ
What is the maximum output frequency supported by SI5338Q-B04428-GMR?
The SI5338Q-B04428-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) per the device's MultiSynth™ architecture.
Does SI5338Q-B04428-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?
Yes, SI5338Q-B04428-GMR is explicitly qualified for PCIe Gen 4 SRNS mode with 0.11–0.32 ps RMS jitter (10 kHz–50 MHz) when configured with PLL bandwidth of 2–5 MHz and CDR set to 10 MHz, as verified in Skyworks' AN562 and PCIe Clock Jitter Tool validation.
Can SI5338Q-B04428-GMR generate four different frequencies simultaneously?
Yes, SI5338Q-B04428-GMR uses four independent MultiSynth™ engines to synthesize four distinct output frequencies-from 0.16 MHz to 710 MHz-with zero ppm error. Each output is fully configurable for format, voltage, phase, and spread spectrum independently.
What reference inputs does SI5338Q-B04428-GMR accept?
SI5338Q-B04428-GMR accepts six reference inputs: differential (IN1/IN2, IN5/IN6) up to 710 MHz; single-ended (IN3/IN4) for CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz); and external crystals (8–30 MHz) directly connected to IN1/IN2 with on-chip load capacitance tuning.
Is ClockBuilder Pro software required to configure SI5338Q-B04428-GMR?
No-ClockBuilder Pro is optional but strongly recommended. SI5338Q-B04428-GMR can be configured via standard I²C commands (SMBus-compatible), but ClockBuilder Pro provides GUI-based register mapping, jitter simulation, PCIe compliance checks, and one-click configuration file generation for production programming.
SI5338Q-B04428-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338Q-B04428-GMR FAQ
1.How can I place an order for SI5338Q-B04428-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338Q-B04428-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338Q-B04428-GMR reliable?
The price and inventory of SI5338Q-B04428-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338Q-B04428-GMR is usually 5 days.
3.What payment methods are accepted for SI5338Q-B04428-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338Q-B04428-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338Q-B04428-GMR?
SI5338Q-B04428-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338Q-B04428-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338Q-B04428-GMR?
For technical support, including SI5338Q-B04428-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338Q-B04428-GMR requirements.
6.How does Aetrix verify that SI5338Q-B04428-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338Q-B04428-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338Q-B04428-GMR meets industry standards.
7.What is the process for return or replacement of SI5338Q-B04428-GMR?
All SI5338Q-B04428-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338Q-B04428-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338Q-B04428-GMR part is unused and in its original packaging.
Return procedure for SI5338Q-B04428-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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