Skyworks Solutions Inc. SI5338Q-B04735-GM
- Part No.:
- SI5338Q-B04735-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338Q-B04735-GM.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5338Q-B04735-GM from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in Ethernet switch/router, PCIe, and FPGA clocking systems.
For engineers reviewing the SI5338Q-B04735-GM datasheet, SI5338Q-B04735-GM pinout, SI5338Q-B04735-GM application, or SI5338Q-B04735-GM equivalent, key selection criteria include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), low-power 4×4 mm 24-QFN package, and I²C/SMBus programmability with ClockBuilder Pro software integration.
Technical Context
The SI5338Q-B04735-GM implements a two-stage PLL architecture: a high-performance synthesis stage (VCO + MultiSynth™ dividers) followed by a flexible output stage with independent format and voltage control per driver. Its patented MultiSynth™ enables fractional-N frequency synthesis with 1 ppb resolution and true zero-ppm accuracy on all outputs.
It supports six input types - external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz) - and delivers up to four differential outputs (LVPECL/LVDS/HCSL/CML) or eight single-ended outputs (CMOS/SSTL/HSTL), with independent phase adjustment (<20 ps steps) and glitchless frequency increment/decrement (1 ppm steps).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count & type | 4 independent differential clock outputs (CLK0A/B through CLK3A/B), configurable as LVPECL/LVDS/HCSL/CML or CMOS/SSTL/HSTL |
| Phase jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz), meeting PCIe Gen 3 SRNS and Gen 4 common clock requirements |
| Frequency range | 0.16–710 MHz per output; supports simultaneous >350 MHz outputs only at Fvco/4 and Fvco/6 |
| Input reference support | Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) |
| Supply & power | Core: 1.8/2.5/3.3 V (±10%); output buffers: 1.4–3.63 V; core current typ. 45 mA @ 100 MHz on all outputs |
| Operating temperature | –40 to +85 °C, qualified for industrial and telecom line card environments |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad |
Pinout & Package
SI5338Q-B04735-GM uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated in Skyworks Rev. 1.6 datasheet Figure 1 (Top View).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential input pairs | Accept AC-coupled differential clocks up to 710 MHz; require external 100 Ω termination |
| IN3, IN4 | Single-ended input pins | Support CMOS/SSTL/HSTL inputs (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A–CLK3B | Differential output pairs | Four independent output drivers; each configurable for LVPECL/LVDS/HCSL/CML with selectable VDDOx |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.5/1.8/2.5/3.3 V supply per output bank; enable mixed-voltage system interfacing |
| VDD | Core supply | Single 1.8/2.5/3.3 V core rail; PSRR optimized for noise immunity |
| SCL, SDA | I²C interface | Standard SMBus-compatible serial interface (up to 400 kHz); supports ClockBuilder Pro programming |
| INTR | Interrupt output | Open-drain status pin indicating loss-of-lock or loss-of-signal events |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ frequency synthesis | Enables independent, any-frequency generation (0.16–710 MHz) on all four outputs with 1 ppb resolution and 0 ppm error |
| PCIe Gen 1–4 compliance | Fully meets PCIe Gen 3 SRNS and Gen 4 common clock jitter specs (0.11–0.45 ps RMS) without external filtering |
| Independent output configuration | Each of four output banks supports separate signal format (LVDS/LVPECL/HCSL/CMOS), voltage (1.5–3.3 V), and termination |
| Glitchless frequency tuning | Hardware-supported ±1 ppm frequency increment/decrement via dedicated pins, enabling real-time dynamic clock scaling |
| Programmable spread spectrum | Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, 5–350 MHz frequency range |
| Zero-delay mode support | External feedback path allows synchronous clock distribution with matched input-to-output propagation delay (2.5–4 ns) |
Applications
| Ethernet Switch/Router Timing | PCIe Gen 3/4 Clock Distribution |
|---|---|
Use Scenario: High-density 1/10 GbE switching fabric requiring synchronized clocks across multiple PHYs, MACs, and packet processors. IC Role / Device Role / Timing Role: Quad clock generator providing four independent, low-jitter clocks (e.g., 125 MHz, 156.25 MHz, 312.5 MHz, 625 MHz) with precise phase alignment. Use Value: Eliminates need for four discrete oscillators; reduces board area and BOM count while maintaining sub-1 ps RMS jitter required for 10 GbE IEEE 802.3ae compliance. |
Use Scenario: Server motherboard or add-in card implementing PCIe Gen 3 or Gen 4 root complex and endpoints. IC Role / Device Role / Timing Role: Common clock source delivering 100 MHz differential HCSL clocks compliant with PCIe Base Spec 3.0/4.0 SRNS and common clock modes. Use Value: Meets PCIe Gen 4 total jitter limit (0.45 ps RMS) and supports both common clock and SRNS topologies from a single device. |
| Broadcast Video/Audio Synchronization | FPGA & Processor Clocking |
Use Scenario: SMPTE ST 2082/ST 2081 video over IP infrastructure requiring frame-accurate timing across multiple encoders, decoders, and routers. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating exact multiples of 27 MHz, 74.25 MHz, or 148.5 MHz with <20 ps phase step resolution. Use Value: Enables deterministic phase alignment across distributed video nodes without external delay lines or manual trimming. |
Use Scenario: Heterogeneous compute platform integrating FPGA, ARM SoC, and DDR4 memory subsystems with disparate clock domain requirements. IC Role / Device Role / Timing Role: Centralized clock hub supplying 100 MHz processor clock, 300 MHz FPGA logic clock, 1200 MHz DDR4 PHY clock, and 25 MHz debug UART clock. Use Value: Supports mixed-signal voltage domains (1.8 V FPGA I/O, 1.2 V DDR4, 3.3 V UART) via independent VDDOx supplies and format flexibility. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D06989-GM | Higher integration: 8 outputs, integrated jitter cleaner, lower jitter (0.23 ps RMS), supports JESD204B deterministic latency | Targeted at JESD204B SerDes, radar, and high-speed data converter systems where ultra-low jitter and deterministic delay are mandatory | Select when system requires <0.3 ps RMS jitter or JESD204B compliance; not drop-in due to different pinout and register map |
| ICS8430I-01T | Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; 3.3 V only; no spread spectrum or phase adjustment | Suitable for cost-sensitive, static-clock applications like legacy telecom line cards where reconfiguration is unnecessary | Choose for simple, low-cost replacement of four fixed-frequency oscillators; lacks programmability and multi-format flexibility of SI5338Q-B04735-GM |
Compared with Si5332A-D06989-GM and ICS8430I-01T, the SI5338Q-B04735-GM uniquely balances field-programmability, wide frequency coverage (0.16–710 MHz), mixed-signal voltage support, and PCIe Gen 4 readiness in a compact 4×4 mm footprint-making it optimal for adaptable, multi-standard platforms where design reuse and future-proofing matter.
Availability
SI5338Q-B04735-GM is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe Gen 3/4 clock distribution, and FPGA & processor clocking requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for SI5338Q-B04735-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.
The Si5338 product line was designed to replace multiple discrete oscillators with a single, software-configurable clock generator for high-speed digital systems-including PCIe, Ethernet, broadcast video, and FPGA-based platforms-emphasizing low jitter, flexibility, and space savings.
FAQ
What is the primary function of the SI5338Q-B04735-GM?
The SI5338Q-B04735-GM is an I²C-programmable quad clock generator IC that synthesizes four independent, low-jitter output clocks from a single reference input. It replaces up to four crystal oscillators in systems requiring precise, configurable timing-such as PCIe, Ethernet switches, and FPGA platforms-while supporting frequencies from 0.16 MHz to 710 MHz per output with 0 ppm accuracy.
Does the SI5338Q-B04735-GM support PCIe Gen 4 timing requirements?
Yes, the SI5338Q-B04735-GM meets PCIe Gen 4 common clock jitter specifications with 0.15–0.45 ps RMS (12 kHz–20 MHz), verified per PCI-SIG Base Specification 4.0 rev. 0.5. It achieves this using its MultiSynth™ architecture and optimized PLL loop bandwidth (2–4 MHz), making it suitable for server motherboards and high-speed add-in cards without external jitter cleaning.
Can the SI5338Q-B04735-GM generate different output formats simultaneously?
Yes, the SI5338Q-B04735-GM supports mixed output formats across its four drivers-for example, LVDS on CLK0A/B, HCSL on CLK1A/B, CMOS on CLK2A, and SSTL on CLK3A-each with independent VDDOx supply (1.5/1.8/2.5/3.3 V). This enables direct interfacing with diverse logic families (FPGA I/O, DDR4, ASICs) without level-shifting components.
How is the SI5338Q-B04735-GM programmed and configured?
The SI5338Q-B04735-GM is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. This GUI tool auto-generates configuration files, validates timing constraints, and exports register maps for production programming-enabling rapid prototyping and field updates without hardware changes.
What package and thermal characteristics does the SI5338Q-B04735-GM have?
The SI5338Q-B04735-GM uses a 24-pin QFN package (4 × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Its thermal resistance is θJA = 37 °C/W (still air) and θJC = 10 °C/W, supporting reliable operation at full load across –40 to +85 °C. The small footprint and low 45 mA typical core current make it ideal for space-constrained, thermally sensitive designs.
SI5338Q-B04735-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338Q-B04735-GM FAQ
1.How can I place an order for SI5338Q-B04735-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338Q-B04735-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338Q-B04735-GM reliable?
The price and inventory of SI5338Q-B04735-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338Q-B04735-GM is usually 5 days.
3.What payment methods are accepted for SI5338Q-B04735-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338Q-B04735-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338Q-B04735-GM?
SI5338Q-B04735-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338Q-B04735-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338Q-B04735-GM?
For technical support, including SI5338Q-B04735-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338Q-B04735-GM requirements.
6.How does Aetrix verify that SI5338Q-B04735-GM is sourced from the original manufacturer or authorized distributors?
All SI5338Q-B04735-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338Q-B04735-GM meets industry standards.
7.What is the process for return or replacement of SI5338Q-B04735-GM?
All SI5338Q-B04735-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338Q-B04735-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338Q-B04735-GM part is unused and in its original packaging.
Return procedure for SI5338Q-B04735-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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