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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338Q-B05203-GM

Name: SI5338Q-B05203-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338Q-B05203-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338Q-B05203-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338Q-B05203-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338Q-B05203-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis with 0 ppm precision per output. It delivers four independent differential or single-ended clocks (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) across 0.16–710 MHz, supports PCIe Gen 1–4 common clock and SRNS compliance, and operates from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package for FPGA, processor, and Ethernet switch timing.

For engineers reviewing the SI5338Q-B05203-GM datasheet, SI5338Q-B05203-GM pinout, SI5338Q-B05203-GM application, or SI5338Q-B05203-GM equivalent, key selection criteria include its 0.7 ps RMS typical phase jitter, independent per-output voltage (1.5–3.3 V), glitchless 1 ppm frequency increment/decrement, <20 ps phase step resolution, and support for external crystal (8–30 MHz) or wide-range differential inputs (5–710 MHz).

Technical Context

The SI5338Q-B05203-GM integrates a dual-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. Its synthesis engine enables true any-frequency generation with integer- or fractional-N division, supporting simultaneous outputs at non-harmonically related frequencies up to 710 MHz.

It features full I²C/SMBus programmability, loss-of-lock and loss-of-signal alarms, independent output enable (OEB), and flexible input options including differential (IN1/IN2/IN5/IN6), single-ended CMOS (IN3/IN4), and external crystal (IN1/IN2). The device supports zero-delay mode via external feedback and offers spread-spectrum clocking (0.5–5.0% spread, 33–63 kHz modulation) on any output.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 independent differential or single-ended outputs (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL)
Frequency range	0.16–710 MHz per output; supports two >350 MHz outputs simultaneously (Fvco/4 and Fvco/6)
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); PCIe Gen 4 compliant at 0.15–0.45 ps RMS
Input reference	External crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating temperature	–40 °C to +85 °C ambient

Pinout & Package

SI5338Q-B05203-GM is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family specification.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential clock inputs	Accept AC-coupled differential reference signals up to 710 MHz; require external 100 Ω termination
IN3, IN4	Single-ended clock inputs	Support CMOS/SSTL/HSTL inputs (5–350 MHz); internally biased; accept DC-coupled signals
CLK0A–CLK3B	Differential output pairs	Four fully independent output drivers; each pair configurable as LVPECL/LVDS/HCSL/CML with selectable VDDO
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V supplies per output bank; enable mixed-voltage system interfacing
VDD	Core supply	Single 1.8/2.5/3.3 V supply powering PLL, logic, and MultiSynth engines
SCL, SDA	I²C interface	Standard SMBus-compatible serial interface (up to 400 kHz) for configuration and status monitoring
INTR	Interrupt output	Open-drain alarm signal indicating loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables independent, zero-ppm-accuracy frequency generation on all four outputs without external crystals or VCXOs
Per-output voltage control	Each of four output banks powered by separate VDDO pins (1.5/1.8/2.5/3.3 V), enabling direct interface to mixed-voltage FPGAs and processors
Glitchless frequency tuning	Hardware-supported 1 ppm frequency increment/decrement with sub-ns update time, eliminating clock interruptions during dynamic scaling
Programmable phase offset	±45 ns initial phase adjustment per output with <20 ps step resolution for precise inter-clock alignment in multi-lane systems
PCIe Gen 4 compliance	Meets PCIe Base Spec 4.0 jitter requirements (0.15–0.45 ps RMS) in common clock mode with 2–5 MHz PLL bandwidth

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric card. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned clocks-one per switch port-with independent SSC control to reduce EMI. Use Value: Eliminates need for four discrete oscillators; meets PCIe Gen 4 SRNS jitter spec (≤0.32 ps RMS) while enabling per-port spread-spectrum tuning.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs and MACs on a carrier-grade Ethernet line card. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant rates from a single 25 MHz crystal reference. Use Value: Achieves 0.7 ps RMS jitter across all outputs-below 1 ps RMS requirement for 25G KR-without custom PLL loop tuning per channel.
FPGA Processor Clocking	Broadcast Video Timing
Use Scenario: Supplying 500 MHz system clock, 250 MHz DDR4 memory clock, 100 MHz peripheral clock, and 27 MHz video clock to a Xilinx Versal ACAP. IC Role / Device Role / Timing Role: Configurable quad clock source replacing multiple oscillators and level translators in heterogeneous SoC timing architecture. Use Value: Independent output voltage per bank (1.8 V for DDR4, 1.0 V for core, 3.3 V for legacy peripherals) avoids external level shifters and reduces BOM count.	Use Scenario: Delivering SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz reference clocks to video encoder/decoder ASICs in broadcast infrastructure. IC Role / Device Role / Timing Role: High-precision, low-phase-noise clock generator meeting ITU-R BT.2019 jitter limits (<0.2 UI) for 4K/8K real-time encoding. Use Value: 0.7 ps RMS jitter ensures <0.005° phase error at 148.5 MHz-critical for genlock stability across multi-channel SDI distribution systems.

PCIe Gen 4 Switch Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric card.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned clocks-one per switch port-with independent SSC control to reduce EMI.

Use Value: Eliminates need for four discrete oscillators; meets PCIe Gen 4 SRNS jitter spec (≤0.32 ps RMS) while enabling per-port spread-spectrum tuning.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs and MACs on a carrier-grade Ethernet line card.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant rates from a single 25 MHz crystal reference.

Use Value: Achieves 0.7 ps RMS jitter across all outputs-below 1 ps RMS requirement for 25G KR-without custom PLL loop tuning per channel.

FPGA Processor Clocking

Broadcast Video Timing

Use Scenario: Supplying 500 MHz system clock, 250 MHz DDR4 memory clock, 100 MHz peripheral clock, and 27 MHz video clock to a Xilinx Versal ACAP.

IC Role / Device Role / Timing Role: Configurable quad clock source replacing multiple oscillators and level translators in heterogeneous SoC timing architecture.

Use Value: Independent output voltage per bank (1.8 V for DDR4, 1.0 V for core, 3.3 V for legacy peripherals) avoids external level shifters and reduces BOM count.

Use Scenario: Delivering SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz reference clocks to video encoder/decoder ASICs in broadcast infrastructure.

IC Role / Device Role / Timing Role: High-precision, low-phase-noise clock generator meeting ITU-R BT.2019 jitter limits (<0.2 UI) for 4K/8K real-time encoding.

Use Value: 0.7 ps RMS jitter ensures <0.005° phase error at 148.5 MHz-critical for genlock stability across multi-channel SDI distribution systems.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05203-GM	Higher integration: includes integrated crystal, eliminates external XTAL; lower max output frequency (500 MHz vs. 710 MHz); improved jitter (0.35 ps RMS)	Preferred for space-constrained designs where board area for crystal and load caps must be minimized; less suitable for >500 MHz applications	Select when crystal footprint reduction and guaranteed startup reliability outweigh need for >500 MHz outputs.
ICS853S02AGT	Fixed-frequency, non-programmable; only two LVDS outputs; no I²C interface; higher jitter (1.2 ps RMS); requires external loop filter	Applicable only for static, dual-output clock fanout-not for any-frequency synthesis or PCIe Gen 4 compliance	Choose only for cost-sensitive, low-complexity applications with fixed 100/125 MHz requirements and no phase control needs.

Compared with Si5332A-D05203-GM, SI5338Q-B05203-GM offers broader frequency coverage and external crystal flexibility but lacks integrated resonator; versus ICS853S02AGT, it provides full programmability, four outputs, and PCIe Gen 4 compliance at the cost of higher design complexity and BOM count.

Availability

SI5338Q-B05203-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switch clocking, FPGA processor clocking, and broadcast video timing requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338Q-B05203-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line was designed specifically for high-performance, multi-output clock generation in FPGA, processor, and high-speed serial interface applications-emphasizing low jitter, flexible format support, and field-programmability via I²C.

FAQ

What is the maximum output frequency supported by SI5338Q-B05203-GM?

The SI5338Q-B05203-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs and 350 MHz on HCSL outputs. However, only two unique frequencies above 350 MHz can be generated simultaneously-specifically Fvco/4 and Fvco/6-as defined by the internal VCO architecture. All other outputs are limited to ≤350 MHz in that configuration.

Does SI5338Q-B05203-GM support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, SI5338Q-B05203-GM meets PCIe Gen 4 SRNS jitter requirements (0.11–0.32 ps RMS) when configured with a PLL bandwidth of 2–5 MHz and CDR set to 10 MHz. This mode is validated per PCI-SIG Base Specification 4.0 rev. 0.5 and confirmed in Skyworks' AN562 application note.

Can SI5338Q-B05203-GM generate different output voltages on each of its four outputs?

Yes, SI5338Q-B05203-GM provides independent VDDO0–VDDO3 pins, allowing each output bank to be powered at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct connection to mixed-voltage devices-e.g., 1.8 V for DDR4 PHYs, 3.3 V for legacy peripherals-without external level shifters.

What is the minimum input reference frequency for SI5338Q-B05203-GM in PLL bypass (buffer) mode?

In PLL bypass mode, SI5338Q-B05203-GM supports input frequencies as low as 1 MHz on single-ended inputs (IN3/IN4) and 5 MHz on differential inputs (IN1/IN2/IN5/IN6). Note that loss-of-signal detection is disabled below 5 MHz on differential inputs.

How is phase alignment controlled across the four outputs of SI5338Q-B05203-GM?

SI5338Q-B05203-GM provides programmable initial phase offset (±45 ns range) and fine-grained phase increment/decrement (≤20 ps steps) on each output. Phase alignment is maintained across power cycles when configuration is stored in OTP NVM, and skew between outputs is guaranteed ≤100 ps under matched conditions.

SI5338Q-B05203-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338Q-B05203-GM FAQ

1.How can I place an order for SI5338Q-B05203-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338Q-B05203-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338Q-B05203-GM reliable?

The price and inventory of SI5338Q-B05203-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338Q-B05203-GM is usually 5 days.

3.What payment methods are accepted for SI5338Q-B05203-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338Q-B05203-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338Q-B05203-GM?

SI5338Q-B05203-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338Q-B05203-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338Q-B05203-GM?

For technical support, including SI5338Q-B05203-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338Q-B05203-GM requirements.

6.How does Aetrix verify that SI5338Q-B05203-GM is sourced from the original manufacturer or authorized distributors?

All SI5338Q-B05203-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338Q-B05203-GM meets industry standards.

7.What is the process for return or replacement of SI5338Q-B05203-GM?

All SI5338Q-B05203-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338Q-B05203-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338Q-B05203-GM part is unused and in its original packaging.

Return procedure for SI5338Q-B05203-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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