Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338Q-B05203-GMR

Name: SI5338Q-B05203-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338Q-B05203-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338Q-B05203-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338Q-B05203-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,627

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338Q-B05203-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe switch cards and FPGA-based compute platforms.

For engineers reviewing the SI5338Q-B05203-GMR datasheet, SI5338Q-B05203-GMR pinout, SI5338Q-B05203-GMR application, or SI5338Q-B05203-GMR equivalent, key selection considerations include its MultiSynth™ fractional-N synthesis architecture, independent per-output voltage (1.5–3.3 V), 0.16–710 MHz frequency range per channel, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats.

Technical Context

The SI5338Q-B05203-GMR implements a two-stage PLL architecture: a high-stability integer-N Phase-Locked Loop (Stage 1) locks to one of six input references (crystal, CMOS, SSTL/HSTL, or differential), followed by four independent MultiSynth™ fractional-N synthesis blocks (Stage 2) generating each output. Each MultiSynth supports programmable initial phase offset (±45 ns), 20 ps step phase increment/decrement, and spread-spectrum modulation (0.5–5.0% down-spread, 33–63 kHz).

It features loss-of-lock and loss-of-signal monitoring, I²C/SMBus-compatible configuration, external feedback mode for zero-delay operation, and independent output enable control. The device operates across –40 to +85 °C and achieves <10 ps pk-pk cycle-cycle jitter and <20 ps output-to-output skew under matched conditions.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); enables PCIe Gen 4 common clock compliance
Output Count & Type	4 independent outputs; supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats
Frequency Range	0.16–710 MHz per output; includes PCIe Gen 4 (100 MHz HCSL) and 156.25 MHz Ethernet
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, GMR suffix denotes green packaging
Operating Temperature	–40 to +85 °C ambient; validated for industrial and telecom line card deployment

Pinout & Package

SI5338Q-B05203-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per Si5338 family: IN1/IN2 (differential ref 1), IN3/IN4 (single-ended ref 2), IN5/IN6 (differential ref 3), CLK0A/CLK0B through CLK3A/CLK3B (four differential output pairs), VDDO0–VDDO3 (independent output supply pins), VDD (core supply), SCL/SDA (I²C interface), INTR (interrupt output), and RSVD_GND (reserved ground).

Pin/Terminal	Circuit Role	Design Meaning
IN1 / IN2	Differential reference input 1	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination
IN3 / IN4	Single-ended reference input 2	Supports 5–200 MHz CMOS-level clock; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A / CLK0B	Differential output 0	Configurable format (LVPECL/LVDS/HCSL/CML); VDDO0 sets output voltage
CLK1A / CLK1B	Differential output 1	Independent frequency, phase, and format control; supports glitchless 1 ppm step tuning
SCL / SDA	I²C configuration interface	Standard SMBus-compatible 100/400 kHz operation; supports ClockBuilder Pro programming
INTR	Interrupt output	Open-drain status signal indicating loss-of-lock or loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling true zero-ppm accuracy on all outputs
PCIe Gen 1–4 compliance	Validated for Common Clock (Gen 1/2/3/4) and Gen 3 SRNS; meets PCIe 4.0 jitter spec (≤0.45 ps RMS)
Per-output voltage control	VDDO0–VDDO3 allow mixed-voltage system interfacing (e.g., 1.8 V FPGA + 3.3 V PHY)
Glitchless frequency tuning	Independent ±1 ppm step increment/decrement via pin or I²C without output interruption
Programmable phase offset	±45 ns adjustment per output in <20 ps steps; enables precise inter-channel skew alignment
Spread-spectrum capability	Configurable on any output: 0.5–5.0% down-spread, 33–63 kHz modulation rate

Applications

PCIe Switch Timing	FPGA Clock Distribution
Use Scenario: High-density PCIe Gen 4 switch card requiring four synchronized 100 MHz HCSL clocks with sub-1 ps jitter. IC Role / Device Role / Timing Role: Quad clock generator providing independent, low-jitter reference clocks to PCIe root complex, endpoint, and switch fabric logic. Use Value: Meets PCIe Gen 4 common clock TJ spec (<33.6 ps pk-pk) and eliminates need for four discrete oscillators, reducing BOM count and layout area.	Use Scenario: Xilinx Versal or Intel Agilex FPGA platform needing multiple domain-specific clocks (e.g., 300 MHz PL, 150 MHz PS, 125 MHz GTY, 100 MHz DDR). IC Role / Device Role / Timing Role: Programmable frequency translator and buffer delivering precisely phased, format-matched clocks to FPGA I/O banks and transceivers. Use Value: Enables single-chip clock tree with independent voltage control per output, eliminating level-shifting components and simplifying power domain isolation.
Ethernet Line Card	Broadcast Video Sync
Use Scenario: 10 GbE/25 GbE line card with SFP28 interfaces requiring 156.25 MHz and 312.5 MHz clocks with OC-12–compliant jitter. IC Role / Device Role / Timing Role: Dual-frequency clock source supporting both Ethernet PHY and MAC layers with deterministic jitter performance. Use Value: Achieves ≤0.7 ps RMS OC-12 random jitter at 155.52 MHz, satisfying ITU-T G.823/G.8262 requirements for telecom-grade synchronization.	Use Scenario: SMPTE ST 2110 video over IP gateway requiring genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks with <10 ps skew. IC Role / Device Role / Timing Role: Multi-format clock generator delivering synchronized LVDS and CMOS clocks to video encoder, decoder, and packetizer ASICs. Use Value: Independent phase adjustment (<20 ps steps) and output skew <100 ps ensure frame-accurate A/V alignment across multi-channel video pipelines.

PCIe Switch Timing

FPGA Clock Distribution

Use Scenario: High-density PCIe Gen 4 switch card requiring four synchronized 100 MHz HCSL clocks with sub-1 ps jitter.

IC Role / Device Role / Timing Role: Quad clock generator providing independent, low-jitter reference clocks to PCIe root complex, endpoint, and switch fabric logic.

Use Value: Meets PCIe Gen 4 common clock TJ spec (<33.6 ps pk-pk) and eliminates need for four discrete oscillators, reducing BOM count and layout area.

Use Scenario: Xilinx Versal or Intel Agilex FPGA platform needing multiple domain-specific clocks (e.g., 300 MHz PL, 150 MHz PS, 125 MHz GTY, 100 MHz DDR).

IC Role / Device Role / Timing Role: Programmable frequency translator and buffer delivering precisely phased, format-matched clocks to FPGA I/O banks and transceivers.

Use Value: Enables single-chip clock tree with independent voltage control per output, eliminating level-shifting components and simplifying power domain isolation.

Ethernet Line Card

Broadcast Video Sync

Use Scenario: 10 GbE/25 GbE line card with SFP28 interfaces requiring 156.25 MHz and 312.5 MHz clocks with OC-12–compliant jitter.

IC Role / Device Role / Timing Role: Dual-frequency clock source supporting both Ethernet PHY and MAC layers with deterministic jitter performance.

Use Value: Achieves ≤0.7 ps RMS OC-12 random jitter at 155.52 MHz, satisfying ITU-T G.823/G.8262 requirements for telecom-grade synchronization.

Use Scenario: SMPTE ST 2110 video over IP gateway requiring genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks with <10 ps skew.

IC Role / Device Role / Timing Role: Multi-format clock generator delivering synchronized LVDS and CMOS clocks to video encoder, decoder, and packetizer ASICs.

Use Value: Independent phase adjustment (<20 ps steps) and output skew <100 ps ensure frame-accurate A/V alignment across multi-channel video pipelines.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05203-GM	Higher integration: integrated crystal, lower jitter (0.35 ps RMS), but fixed 4-output LVDS-only; no HCSL/CMOS support	Best for space-constrained, crystal-less designs where only LVDS outputs are needed and PCIe Gen 5 readiness is required	Select when board area is critical and output format flexibility is not required; not drop-in due to different pinout and no I²C address compatibility
ICS853S02AG-01T	Non-programmable, fixed-frequency quad LVDS buffer; 1.2 ps RMS jitter; no frequency synthesis or I²C interface	Suitable only for static clock fanout; lacks any-frequency generation, phase control, or spread spectrum	Choose only for simple clock distribution where frequencies are known at design stage and no runtime reconfiguration is needed

Compared with SI5338Q-B05203-GMR, Si5332A-D05203-GM offers superior jitter and integrated crystal but sacrifices output format flexibility and I²C programmability, while ICS853S02AG-01T provides low-cost fanout only-neither matches the SI5338Q-B05203-GMR's balance of programmability, multi-format support, and PCIe Gen 4 compliance.

Availability

SI5338Q-B05203-GMR is available at Aetrix Electronics and suitable for PCIe switch timing, FPGA clock distribution, Ethernet line cards, and broadcast video sync applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338Q-B05203-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clocking expertise.

The Si5338 product line was designed for high-performance, multi-protocol timing in datacenter, networking, and communications equipment-specifically addressing the need for flexible, low-jitter clock synthesis in systems with heterogeneous voltage domains and evolving serial interface standards.

FAQ

What is the maximum output frequency supported by SI5338Q-B05203-GMR?

The SI5338Q-B05203-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 250 MHz on HCSL, and 200 MHz on CMOS. However, only two unique frequencies above 350 MHz can be simultaneously generated (Fvco/4 and Fvco/6), as defined by the MultiSynth architecture. All frequencies are synthesized with 0 ppm precision using fractional-N division.

Does SI5338Q-B05203-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338Q-B05203-GMR is explicitly validated for PCIe Gen 4 Common Clock operation, delivering ≤0.45 ps RMS jitter at 100 MHz HCSL output under specified test conditions (PLL BW 2–4 MHz, CDR = 10 MHz). This meets the PCI-SIG Base Specification 4.0 requirement for total jitter <33.6 ps pk-pk.

Can SI5338Q-B05203-GMR generate different output voltages on each channel?

Yes, SI5338Q-B05203-GMR provides independent VDDO0–VDDO3 supply pins, allowing each of its four outputs to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage devices-for example, driving a 1.8 V FPGA bank and a 3.3 V Ethernet PHY from the same IC without external level shifters.

How is SI5338Q-B05203-GMR programmed, and is ClockBuilder Pro required?

SI5338Q-B05203-GMR is programmed via its I²C/SMBus interface (SCL/SDA pins) using register writes. While ClockBuilder Pro is the official Skyworks GUI tool for configuration and .cmb file generation, custom firmware can directly write to the device's 256-byte register map. Pre-programmed OTP versions are also available, but SI5338Q-B05203-GMR uses factory-default configuration and requires in-system programming.

What reference inputs does SI5338Q-B05203-GMR accept?

SI5338Q-B05203-GMR accepts six reference inputs: two differential (IN1/IN2, IN5/IN6; 5–710 MHz), two single-ended CMOS (IN3/IN4; 5–200 MHz), and two differential-capable SSTL/HSTL inputs (IN3/IN4 with proper biasing; 5–350 MHz). It also supports external 8–30 MHz crystals connected to IN1/IN2 with on-chip load capacitance tuning.

SI5338Q-B05203-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338Q-B05203-GMR FAQ

1.How can I place an order for SI5338Q-B05203-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338Q-B05203-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338Q-B05203-GMR reliable?

The price and inventory of SI5338Q-B05203-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338Q-B05203-GMR is usually 5 days.

3.What payment methods are accepted for SI5338Q-B05203-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338Q-B05203-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338Q-B05203-GMR?

SI5338Q-B05203-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338Q-B05203-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338Q-B05203-GMR?

For technical support, including SI5338Q-B05203-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338Q-B05203-GMR requirements.

6.How does Aetrix verify that SI5338Q-B05203-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338Q-B05203-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338Q-B05203-GMR meets industry standards.

7.What is the process for return or replacement of SI5338Q-B05203-GMR?

All SI5338Q-B05203-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338Q-B05203-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338Q-B05203-GMR part is unused and in its original packaging.

Return procedure for SI5338Q-B05203-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…