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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338Q-B05247-GM

Name: SI5338Q-B05247-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338Q-B05247-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338Q-B05247-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338Q-B05247-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338Q-B05247-GM from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338Q-B05247-GM datasheet, SI5338Q-B05247-GM pinout, SI5338Q-B05247-GM application, or SI5338Q-B05247-GM equivalent, key selection criteria include output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL), independent per-output voltage (1.5–3.3 V), any-frequency synthesis capability (0.16–710 MHz), and PCIe/10GbE/FC jitter compliance.

Technical Context

The SI5338Q-B05247-GM implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving a configurable output buffer. Its input supports eight clock sources - including external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz) - enabling flexible system-level clock tree integration.

Each output driver supports independent frequency, format, voltage, phase offset (<20 ps step), and spread-spectrum modulation (0.5–5.0% at 33–63 kHz). The device features loss-of-lock and loss-of-signal alarms, I²C/SMBus programmability, and zero-delay mode via external feedback - all managed through on-chip OTP NVM and RAM-based runtime configuration.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typ (12 kHz–20 MHz); meets PCIe Gen 3 SRNS & Gen 4 common clock jitter requirements
Output Frequency Range	0.16–710 MHz per channel; supports integer/fractional synthesis with 1 ppb resolution
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Output Formats	LVPECL, LVDS, HCSL, CML, CMOS, SSTL, HSTL - each configurable per channel
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently selectable 1.5/1.8/2.5/3.3 V
Operating Temperature	–40 to +85 °C; qualified for industrial and telecom line card environments
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture-sensitive level 3

Pinout & Package

SI5338Q-B05247-GM is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin 1 is top-left corner (IN1), pin numbering proceeds counterclockwise. Package complies with JEDEC MO-220, with 0.5 mm lead pitch and 0.8 mm max height.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential clock inputs	Accept AC-coupled LVDS/LVPECL/CML references up to 710 MHz; require external 100 Ω termination
IN3, IN4	Single-ended clock inputs	Support CMOS/SSTL/HSTL signals (5–350 MHz); internally biased; 20 kΩ pull-up/pull-down configurable
CLK0A–CLK3B	Differential output pairs	Four independent output channels (CLK0–CLK3), each with A/B complementary pins; support LVPECL/LVDS/HCSL/CML
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V supplies per output bank; enable mixed-voltage clock distribution
VDD	Core supply	Single 1.8/2.5/3.3 V core rail; PSRR > 60 dB across 10 kHz–100 MHz
SCL, SDA	I²C interface	Standard SMBus-compatible 100/400 kHz interface; supports multi-drop addressing and interrupt-driven programming
INTR	Interrupt output	Open-drain status indicator for loss-of-lock, loss-of-signal, or configuration error events
RSVD_GND	Reserved ground	Internal test pin; must be connected to GND per layout guidelines to ensure thermal and EMI performance

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers deliver true zero-ppm accuracy on all outputs without external components
PCIe Gen 4 compliance	0.15–0.45 ps RMS jitter in common clock mode satisfies PCIe Base Spec 4.0 rev 0.5 requirements
Per-output voltage control	Each of four output banks powered separately (1.5/1.8/2.5/3.3 V), enabling direct interfacing with mixed-voltage FPGAs and ASICs
Glitchless frequency tuning	Independent 1 ppm-step increment/decrement via pin or I²C, with sub-1 ns update latency for dynamic rate adaptation
Programmable phase offset	±45 ns range with <20 ps step resolution per output, supporting precise skew alignment in SerDes lanes
Spread-spectrum modulation	Configurable down-spread (0.5–5.0%) at 33–63 kHz on any output to reduce EMI peak emissions in dense PCB layouts

Applications

PCIe Gen 3/4 Switch Timing	Ethernet Switch/Routing
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 3/4 switch ICs in a data center fabric card. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched phase alignment. Use Value: Eliminates need for four discrete oscillators; reduces board area by 65% and improves jitter margin by 0.2 ps RMS vs. legacy solutions.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and packet processors in carrier-grade Ethernet switches. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant rates from a single 25 MHz crystal reference. Use Value: Enables single-reference clock tree design; avoids external dividers/multipliers and reduces BOM count by 7 parts per switch ASIC.
Broadcast Video Timing	FPGA/ASIC Clocking
Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) pixel clock (270 MHz), AES audio clock (48 kHz), and genlock reference (10 MHz) in 4K/8K video processing hardware. IC Role / Device Role / Timing Role: Multi-format clock source generating differential LVDS, single-ended CMOS, and low-frequency reference simultaneously. Use Value: Supports mixed-signal timing domains in one IC; eliminates inter-channel skew between video/audio subsystems (<100 ps).	Use Scenario: Supplying 500 MHz GTY transceiver reference, 250 MHz logic clock, and 100 MHz configuration clock to Xilinx Versal ACAP with mixed I/O voltage requirements. IC Role / Device Role / Timing Role: Configurable quad clock generator with independent VDDO per output bank (1.8 V, 1.2 V, 2.5 V). Use Value: Directly drives diverse FPGA I/O standards without level shifters; reduces power delivery complexity and layout congestion.

PCIe Gen 3/4 Switch Timing

Ethernet Switch/Routing

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 3/4 switch ICs in a data center fabric card.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched phase alignment.

Use Value: Eliminates need for four discrete oscillators; reduces board area by 65% and improves jitter margin by 0.2 ps RMS vs. legacy solutions.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs and packet processors in carrier-grade Ethernet switches.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant rates from a single 25 MHz crystal reference.

Use Value: Enables single-reference clock tree design; avoids external dividers/multipliers and reduces BOM count by 7 parts per switch ASIC.

Broadcast Video Timing

FPGA/ASIC Clocking

Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) pixel clock (270 MHz), AES audio clock (48 kHz), and genlock reference (10 MHz) in 4K/8K video processing hardware.

IC Role / Device Role / Timing Role: Multi-format clock source generating differential LVDS, single-ended CMOS, and low-frequency reference simultaneously.

Use Value: Supports mixed-signal timing domains in one IC; eliminates inter-channel skew between video/audio subsystems (<100 ps).

Use Scenario: Supplying 500 MHz GTY transceiver reference, 250 MHz logic clock, and 100 MHz configuration clock to Xilinx Versal ACAP with mixed I/O voltage requirements.

IC Role / Device Role / Timing Role: Configurable quad clock generator with independent VDDO per output bank (1.8 V, 1.2 V, 2.5 V).

Use Value: Directly drives diverse FPGA I/O standards without level shifters; reduces power delivery complexity and layout congestion.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05289-GM	Higher integration: includes integrated crystal, lower jitter (0.35 ps RMS), supports up to 10 outputs	Targeted at space-constrained systems requiring ultra-low jitter and reduced external BOM	Preferred when crystal integration and sub-0.4 ps jitter are required; not drop-in due to different pinout and higher cost
ICS8430I-01LG	Fixed-frequency, non-programmable; 4 LVDS outputs only; 1.2 ps RMS jitter; no I²C interface	Suitable for cost-sensitive, static-clock applications where frequency agility is unnecessary	Select when design requires guaranteed fixed frequencies and minimal firmware overhead; lacks any-frequency synthesis and voltage flexibility

Compared with Si5332A-D05289-GM, SI5338Q-B05247-GM offers broader input reference support and lower system cost without integrated crystal; versus ICS8430I-01LG, it enables field-upgradable timing configurations and mixed-signal voltage compatibility at the expense of higher software integration effort.

Availability

SI5338Q-B05247-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, 10GbE routing infrastructure, and broadcast video equipment requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338Q-B05247-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, Fibre Channel, and broadcast video, targeting systems requiring flexible, multi-rate timing with minimal footprint.

FAQ

What is the maximum output frequency supported by SI5338Q-B05247-GM?

The SI5338Q-B05247-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) per the device's synthesis architecture.

Does SI5338Q-B05247-GM support PCIe Gen 4 Common Clock compliance?

Yes, SI5338Q-B05247-GM achieves 0.15–0.45 ps RMS jitter in PCIe Gen 4 common clock mode (PLL BW 2–5 MHz, CDR = 10 MHz), meeting PCI-SIG Base Specification 4.0 rev 0.5 requirements. This is verified using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4.

Can SI5338Q-B05247-GM generate different output voltages on each channel?

Yes, SI5338Q-B05247-GM provides independent VDDO0–VDDO3 supplies, allowing each of its four output banks to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct connection to mixed-voltage FPGAs, ASICs, and SerDes PHYs without external level shifters.

How is SI5338Q-B05247-GM programmed in-system?

SI5338Q-B05247-GM is programmed via its I²C/SMBus-compatible interface (SCL/SDA pins) using Skyworks' ClockBuilder Pro software. Configuration can be stored in on-chip OTP memory for autonomous startup or loaded dynamically via host processor during initialization.

What input reference options does SI5338Q-B05247-GM support?

SI5338Q-B05247-GM accepts eight input types: external crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz). Input pins IN1/IN2/IN5/IN6 are differential; IN3/IN4 are single-ended with internal biasing and configurable pull-ups.

SI5338Q-B05247-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338Q-B05247-GM FAQ

1.How can I place an order for SI5338Q-B05247-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338Q-B05247-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338Q-B05247-GM reliable?

The price and inventory of SI5338Q-B05247-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338Q-B05247-GM is usually 5 days.

3.What payment methods are accepted for SI5338Q-B05247-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338Q-B05247-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338Q-B05247-GM?

SI5338Q-B05247-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338Q-B05247-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338Q-B05247-GM?

For technical support, including SI5338Q-B05247-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338Q-B05247-GM requirements.

6.How does Aetrix verify that SI5338Q-B05247-GM is sourced from the original manufacturer or authorized distributors?

All SI5338Q-B05247-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338Q-B05247-GM meets industry standards.

7.What is the process for return or replacement of SI5338Q-B05247-GM?

All SI5338Q-B05247-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338Q-B05247-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338Q-B05247-GM part is unused and in its original packaging.

Return procedure for SI5338Q-B05247-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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