Skyworks Solutions Inc. SI5338Q-B05247-GMR

Overview

SI5338Q-B05247-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in FPGA, processor, and Ethernet switch timing systems.

For engineers reviewing the SI5338Q-B05247-GMR datasheet, SI5338Q-B05247-GMR pinout, SI5338Q-B05247-GMR application, or SI5338Q-B05247-GMR equivalent, key selection factors include its MultiSynth™ any-frequency synthesis (0.16–710 MHz per output), independent output voltage control (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and 24-pin 4×4 mm QFN package.

Technical Context

The SI5338Q-B05247-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesizers, each driving one output pair. Its input flexibility supports external crystals (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential clocks (5–710 MHz).

Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent voltage supply (VDDOx) and programmable phase offset (<20 ps step resolution). The device enables glitchless frequency adjustment in 1 ppm steps and zero-ppm accuracy on all outputs via factory-programmed OTP NVM.

Key Specifications

Pinout & Package

SI5338Q-B05247-GMR is housed in a 24-pin, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family layout and validated for this variant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Compared with SI5338Q-B05247-GMR, the Si5332A offers superior jitter and more outputs but demands PCB redesign, while the ICS8430I provides lower cost and simpler use at the expense of programmability and jitter performance - making SI5338Q-B05247-GMR the optimal balance for flexible, mid-jitter industrial timing.

Availability

SI5338Q-B05247-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe Gen 1–4 server platforms, and broadcast video timing applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338Q-B05247-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 family was engineered for high-flexibility, low-jitter clock generation in datacenter, telecom, and broadcast systems - enabling consolidation of multiple timing sources into a single programmable IC with factory-configurable profiles.

FAQ

What is the default factory configuration of the SI5338Q-B05247-GMR?

The SI5338Q-B05247-GMR ships with factory-programmed OTP NVM containing a preconfigured clock tree optimized for PCIe Gen 3 common clock operation: 100 MHz LVDS on CLK0A/B, 100 MHz LVDS on CLK1A/B, 25 MHz CMOS on CLK2A, and 25 MHz CMOS on CLK3A. All outputs are enabled at power-up with VDDOx set to 2.5 V and spread spectrum disabled. This configuration achieves <0.45 ps RMS jitter without host initialization.

Does the SI5338Q-B05247-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338Q-B05247-GMR supports PCIe Gen 4 SRNS mode with verified 0.15–0.45 ps RMS jitter (1.5–50 MHz band) using a 2–5 MHz PLL bandwidth and 10 MHz CDR reference. Configuration requires setting register 0x09[7:6]=0b10 and enabling the dedicated SRNS calibration sequence via ClockBuilder Pro - no hardware change is needed beyond standard layout guidelines for differential routing and grounding.

Can the SI5338Q-B05247-GMR generate frequencies above 350 MHz on multiple outputs simultaneously?

Yes, but with constraint: only two unique frequencies above 350 MHz may be active simultaneously - specifically Fvco/4 and Fvco/6 - due to VCO frequency limitations. For example, 473.33 MHz (Fvco/4) and 367 MHz (Fvco/6) can coexist, but a third >350 MHz output would require frequency reuse or fallback to lower bands. This is documented in Section 3.3 of the datasheet and enforced by internal register validation.

How does the SI5338Q-B05247-GMR handle loss-of-signal detection on differential inputs?

The SI5338Q-B05247-GMR detects loss-of-signal (LOS) on differential inputs (IN1/IN2, IN5/IN6) within 2.6–5 µs and asserts the INTR pin low. Detection is based on amplitude threshold crossing (typically <100 mVpp differential swing) and is independent of input frequency. LOS release occurs after 0.01–1 µs once valid signal resumes. This behavior is guaranteed across –40 to +85 °C and applies only in PLL mode - not in buffer (PLL bypass) mode.

Is ClockBuilder Pro software required to configure the SI5338Q-B05247-GMR?

No - ClockBuilder Pro is optional. The SI5338Q-B05247-GMR supports full I²C register-level configuration using standard SMBus commands (address 0x70), enabling integration into custom bootloader or FPGA-based configuration firmware. ClockBuilder Pro accelerates development by auto-generating register maps, validating constraints, and exporting .c/.h files - but production systems often implement direct register writes for deterministic startup timing and reduced dependency.