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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338Q-B05298-GM

Name: SI5338Q-B05298-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338Q-B05298-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338Q-B05298-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338Q-B05298-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338Q-B05298-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency outputs (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL signal formats across 1.5–3.3 V output supplies. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338Q-B05298-GM datasheet, SI5338Q-B05298-GM pinout, SI5338Q-B05298-GM application, or SI5338Q-B05298-GM equivalent, key selection criteria include PCIe Gen 4 common-clock jitter (≤0.45 ps RMS), independent per-output voltage configuration, 1 ppm frequency increment/decrement resolution, <20 ps phase step accuracy, and 4×4 mm 24-QFN package compatibility with industrial temperature range (–40 to +85 °C).

Technical Context

The SI5338Q-B05298-GM implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesis blocks. Each output driver supports programmable format, voltage, and spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate), enabling glitchless frequency tuning and precise phase alignment across heterogeneous system clocks.

It accepts six input references-including differential (5–710 MHz), single-ended CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and 8–30 MHz crystals-and provides loss-of-lock and loss-of-signal alarms via dedicated INTR pin. Configuration occurs over I²C/SMBus with nonvolatile OTP memory storing factory- or user-defined settings.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 4 common-clock jitter spec (≤0.45 ps RMS) under specified test conditions
Output Frequency Range	0.16–710 MHz - covers Ethernet (125/156.25 MHz), PCIe (100 MHz), Fibre Channel (1.0625 GHz ÷ 2 = 531.25 MHz), and processor/FPGA clocks
Input Reference Support	8–30 MHz crystal, 5–710 MHz differential, 5–350 MHz SSTL/HSTL - enables flexible system-level clock sourcing
Output Format Flexibility	LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL - allows direct interfacing to diverse logic families without level-shifting
Per-Output Supply Voltage	1.5/1.8/2.5/3.3 V - supports mixed-voltage SoC/FPGA domains from a single device
Package	24-pin QFN, 4 × 4 mm - space-constrained PCBs requiring high-density timing solutions
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line-card environments

Pinout & Package

The SI5338Q-B05298-GM uses a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks Si5338 family specification and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential Input Pairs	Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination
IN3/IN4	Single-Ended Input Pins	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL with internal biasing
CLK0A/CLK0B – CLK3A/CLK3B	Differential Output Pairs	Four independent configurable outputs; each pair supports LVPECL/LVDS/HCSL/CML
VDDO0–VDDO3	Output Buffer Supplies	Independent 1.4–3.63 V supplies per output bank enable mixed-voltage clock distribution
VDD	Core Supply	1.8/2.5/3.3 V ± tolerance; powers PLL, synthesizers, and control logic
SCL/SDA	I²C Interface	Standard SMBus-compatible serial bus for configuration and status readback
INTR	Interrupt Output	Open-drain alarm signal indicating loss-of-lock or loss-of-signal events
RSVD_GND	Reserved Ground	Internal connection to substrate ground; must be tied to PCB ground plane

Key Features

Feature	Design Value
MultiSynth™ Synthesis	Four independent fractional-N synthesizers deliver true zero-ppm frequency accuracy on all outputs
PCIe Gen 4 Compliance	Meets Common Clock jitter requirement (≤0.45 ps RMS) and SRNS mode for Gen 3, enabling drop-in replacement in server/storage designs
Glitchless Frequency Tuning	1 ppm frequency increment/decrement steps with ≤667 ns update time allow real-time clock rate adaptation without output disruption
Sub-20 ps Phase Adjustment	Programmable phase offset (±45 ns range) in <20 ps steps enables precise inter-clock skew management in multi-lane SerDes systems
Flexible Spread Spectrum	Configurable SSC on any output (0.5–5.0% spread, 33–63 kHz rate) reduces EMI without affecting timing margin

Applications

PCIe Gen 4 Server Backplane	Ethernet Switch Timing
Use Scenario: Providing synchronized 100 MHz common clock to multiple PCIe Gen 4 slots and root complexes in a rack-mount server backplane. IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter, phase-aligned reference clocks meeting PCIe Gen 4 common-clock jitter spec (≤0.45 ps RMS). Use Value: Eliminates need for four discrete oscillators while maintaining sub-0.5 ps RMS jitter across all lanes-critical for Gen 4 link training and BER performance.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, switch fabric, and packet buffer controllers in a Layer 3 enterprise switch. IC Role / Device Role / Timing Role: Programmable quad clock source supporting mixed-frequency, mixed-format (LVDS/HCSL/CMOS) clock distribution across ASIC, PHY, and memory interfaces. Use Value: Enables single-device timing for multi-rate Ethernet subsystems with independent voltage and format per output-reducing BOM count and layout complexity.
FPGA-Based Video Processing	Telecom Line Card Synchronization
Use Scenario: Supplying pixel clock (74.25 MHz), reference clock (148.5 MHz), and DDR interface clock (400 MHz) to an FPGA-based broadcast video encoder with strict inter-clock phase alignment. IC Role / Device Role / Timing Role: High-precision, phase-adjustable clock generator supporting sub-20 ps inter-output skew control and independent output voltage scaling. Use Value: Achieves deterministic timing across video pipeline stages-enabling clean frame capture, processing, and output without visible artifacts or sync loss.	Use Scenario: Distributing synchronized 155.52 MHz (OC-3), 622.08 MHz (OC-12), and 2.488 GHz ÷ 2 = 1.244 GHz clocks to multiple DSPs, framer ICs, and SerDes on a SONET/SDH line card. IC Role / Device Role / Timing Role: Low-jitter frequency translator accepting OC-12 reference and generating multiple telecom-standard rates with OC-12-compliant jitter (≤1 ps RMS). Use Value: Maintains network synchronization integrity across distributed line card functions while simplifying clock tree design and reducing jitter accumulation.

PCIe Gen 4 Server Backplane

Ethernet Switch Timing

Use Scenario: Providing synchronized 100 MHz common clock to multiple PCIe Gen 4 slots and root complexes in a rack-mount server backplane.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering low-jitter, phase-aligned reference clocks meeting PCIe Gen 4 common-clock jitter spec (≤0.45 ps RMS).

Use Value: Eliminates need for four discrete oscillators while maintaining sub-0.5 ps RMS jitter across all lanes-critical for Gen 4 link training and BER performance.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, switch fabric, and packet buffer controllers in a Layer 3 enterprise switch.

IC Role / Device Role / Timing Role: Programmable quad clock source supporting mixed-frequency, mixed-format (LVDS/HCSL/CMOS) clock distribution across ASIC, PHY, and memory interfaces.

Use Value: Enables single-device timing for multi-rate Ethernet subsystems with independent voltage and format per output-reducing BOM count and layout complexity.

FPGA-Based Video Processing

Telecom Line Card Synchronization

Use Scenario: Supplying pixel clock (74.25 MHz), reference clock (148.5 MHz), and DDR interface clock (400 MHz) to an FPGA-based broadcast video encoder with strict inter-clock phase alignment.

IC Role / Device Role / Timing Role: High-precision, phase-adjustable clock generator supporting sub-20 ps inter-output skew control and independent output voltage scaling.

Use Value: Achieves deterministic timing across video pipeline stages-enabling clean frame capture, processing, and output without visible artifacts or sync loss.

Use Scenario: Distributing synchronized 155.52 MHz (OC-3), 622.08 MHz (OC-12), and 2.488 GHz ÷ 2 = 1.244 GHz clocks to multiple DSPs, framer ICs, and SerDes on a SONET/SDH line card.

IC Role / Device Role / Timing Role: Low-jitter frequency translator accepting OC-12 reference and generating multiple telecom-standard rates with OC-12-compliant jitter (≤1 ps RMS).

Use Value: Maintains network synchronization integrity across distributed line card functions while simplifying clock tree design and reducing jitter accumulation.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B-GM	Same pinout and core architecture; differs in factory-programmed NVM content and default configuration	Pre-configured for specific reference frequencies and output settings; less flexible for custom multi-frequency synthesis	Select when pre-validated timing profiles reduce bring-up time and firmware overhead
LMK04832ISQE/NOPB	Two-stage jitter cleaner with dual-loop PLL; higher power (120 mA vs. 45 mA typ), larger 64-QFN package	Better suited for ultra-low-jitter cleaning of noisy references rather than pure any-frequency generation	Select when input reference quality is poor and jitter attenuation-not synthesis flexibility-is the primary requirement

Compared with Si5338A-B-GM and LMK04832ISQE/NOPB, the SI5338Q-B05298-GM offers optimal balance of synthesis flexibility, low power (45 mA core), compact 4×4 mm footprint, and PCIe Gen 4 compliance-making it ideal for space-constrained, multi-protocol systems requiring field-programmable clock trees.

Availability

SI5338Q-B05298-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 server backplanes, Ethernet switching infrastructure, FPGA-based broadcast video equipment, and telecom line cards requiring stable component supply and long-term lifecycle support.

Supply support for SI5338Q-B05298-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was designed for high-performance, multi-protocol clock generation in data center, networking, and communications equipment-emphasizing low jitter, configurability, and integration to replace discrete oscillator arrays.

FAQ

What is the maximum output frequency supported by the SI5338Q-B05298-GM?

The SI5338Q-B05298-GM supports differential output frequencies up to 710 MHz (LVPECL/LVDS/CML), 250 MHz (HCSL), and 350 MHz (SSTL/HSTL), with single-ended CMOS outputs up to 200 MHz. These limits are defined by the MultiSynth™ architecture and output driver capabilities, and are confirmed in Skyworks' Si5338 datasheet Table 6. Operation above 350 MHz requires integer-related frequencies and is constrained to Fvco/4 and Fvco/6 outputs per synthesis stage.

Does the SI5338Q-B05298-GM support PCIe Gen 4 Common Clock requirements?

Yes, the SI5338Q-B05298-GM meets PCIe Gen 4 Common Clock total jitter specification with ≤0.45 ps RMS (typical 0.15 ps RMS) when configured per Skyworks' recommended settings (PLL bandwidth 2–4 MHz, CDR = 10 MHz). This compliance is explicitly stated in the datasheet's Table 12 and validated using the Skyworks PCIe Clock Jitter Tool.

Can the SI5338Q-B05298-GM generate different output voltages simultaneously?

Yes, the SI5338Q-B05298-GM supports independent output supply voltages per bank: VDDO0 through VDDO3 can each be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables simultaneous driving of mixed-voltage interfaces-for example, 1.8 V LVDS for an FPGA transceiver and 3.3 V CMOS for a microcontroller-without external level shifters.

How is the SI5338Q-B05298-GM programmed, and is configuration retained after power cycle?

The SI5338Q-B05298-GM is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software. Configuration is stored in one-time-programmable (OTP) nonvolatile memory, so the SI5338Q-B05298-GM retains its settings across power cycles and operates immediately upon power-up without host intervention.

What input reference options does the SI5338Q-B05298-GM support?

The SI5338Q-B05298-GM accepts six input references: differential (5–710 MHz on IN1/IN2 or IN5/IN6), single-ended CMOS (5–200 MHz on IN3/IN4), SSTL/HSTL (5–350 MHz on IN3/IN4), and fundamental-mode crystals (8–30 MHz). All inputs are internally conditioned and selectable via register configuration, enabling robust timing in diverse system architectures.

SI5338Q-B05298-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338Q-B05298-GM FAQ

1.How can I place an order for SI5338Q-B05298-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338Q-B05298-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338Q-B05298-GM reliable?

The price and inventory of SI5338Q-B05298-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338Q-B05298-GM is usually 5 days.

3.What payment methods are accepted for SI5338Q-B05298-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338Q-B05298-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338Q-B05298-GM?

SI5338Q-B05298-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338Q-B05298-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338Q-B05298-GM?

For technical support, including SI5338Q-B05298-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338Q-B05298-GM requirements.

6.How does Aetrix verify that SI5338Q-B05298-GM is sourced from the original manufacturer or authorized distributors?

All SI5338Q-B05298-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338Q-B05298-GM meets industry standards.

7.What is the process for return or replacement of SI5338Q-B05298-GM?

All SI5338Q-B05298-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338Q-B05298-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338Q-B05298-GM part is unused and in its original packaging.

Return procedure for SI5338Q-B05298-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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