Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338Q-B05298-GMR

Name: SI5338Q-B05298-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338Q-B05298-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338Q-B05298-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338Q-B05298-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,207

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338Q-B05298-GMR from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338Q-B05298-GMR datasheet, SI5338Q-B05298-GMR pinout, SI5338Q-B05298-GMR application, or SI5338Q-B05298-GMR equivalent, key selection criteria include PCIe Gen 4 jitter compliance (0.15–0.45 ps RMS), independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ fractional synthesis resolution (1 ppb), spread-spectrum control (0.5–5.0% deviation), and loss-of-lock/loss-of-signal alarm support.

Technical Context

The SI5338Q-B05298-GMR implements a two-stage PLL architecture: Stage 1 uses a VCO with programmable feedback divider (N) and reference dividers (R₀–R₃); Stage 2 applies four independent MultiSynth™ fractional-N synthesizers (M₀–M₃) per output, enabling zero-ppm frequency accuracy and <20 ps phase step resolution. Input flexibility includes differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or 8–30 MHz crystal references.

Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent VDDO supply (1.4–3.63 V), programmable slew rate, and glitchless frequency increment/decrement in 1 ppm steps. External feedback mode enables zero-delay operation, while INTR pin provides loss-of-lock and loss-of-signal status reporting via open-drain output.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 4 common clock jitter spec (≤0.45 ps RMS).
Output Count & Type	4 independent outputs; supports differential (LVPECL/LVDS/HCSL/CML) or single-ended (CMOS/SSTL/HSTL) formats.
Frequency Range	0.16–710 MHz per output; integer/fractional synthesis with 1 ppb resolution.
Input Reference	External crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz).
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: 1.5/1.8/2.5/3.3 V selectable per driver.
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, moisture sensitivity level 3.
Operating Temp	–40 °C to +85 °C ambient; qualified for industrial and telecom line card environments.

Pinout & Package

SI5338Q-B05298-GMR is housed in a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND). The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential input pairs	Accept AC-coupled differential clocks (5–710 MHz); require external 100 Ω termination.
IN3, IN4	Single-ended inputs	Support CMOS/SSTL/HSTL (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD.
CLK0A/CLK0B – CLK3A/CLK3B	Differential output pairs	Four independent output drivers; each configurable for LVPECL/LVDS/HCSL/CML format and voltage.
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V supplies per output bank; enable mixed-voltage system interfacing.
SCL, SDA	I²C interface	SMBus-compatible 100/400 kHz bus; supports write-only programming and readback of status registers.
INTR	Interrupt output	Open-drain alarm signal indicating loss-of-lock or loss-of-signal; requires external pull-up.
VDD	Core supply	1.8/2.5/3.3 V ±10% core power; PSRR optimized for low-noise clock generation.
GND, RSVD_GND	Ground connections	Eight dedicated ground pins including thermal pad; critical for jitter performance and EMI suppression.

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers deliver true zero-ppm frequency accuracy on all outputs with 1 ppb resolution.
PCIe Gen 4 compliance	Meets PCIe Base Spec 4.0 common clock jitter requirement (≤0.45 ps RMS, 10 kHz–50 MHz) without external filtering.
Independent output control	Per-output voltage (1.5/1.8/2.5/3.3 V), format (LVDS/LVPECL/HCSL/CMOS), and spread-spectrum (0.5–5.0%, 33–63 kHz) configuration.
Glitchless frequency tuning	Pin-controlled or I²C-based frequency increment/decrement in 1 ppm steps with ≤667 ns update time above 18 MHz.
Programmable phase offset	±45 ns initial phase adjustment per output with <20 ps step resolution for skew compensation across multi-lane interfaces.
Status monitoring	Dedicated INTR pin reports loss-of-lock and loss-of-signal events; supports real-time system health monitoring.

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: Providing synchronized 100 MHz HCSL clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter reference clocks with matched phase alignment. Use Value: Enables full Gen 4 lane compliance (≤0.45 ps RMS jitter) and eliminates need for four discrete oscillators, reducing BOM count and layout area by 60%.	Use Scenario: Generating 125 MHz LVDS clocks for 10 GbE PHYs and 156.25 MHz CMOS clocks for packet processors in enterprise switches. IC Role / Device Role / Timing Role: Any-frequency clock converter supporting mixed-signal domain bridging between Ethernet MACs, PHYs, and control logic. Use Value: Single-device solution replaces multiple oscillators and level translators; independent VDDO per output allows direct 1.8 V/2.5 V/3.3 V interface without external buffers.
Broadcast Video Timing	Processor & FPGA Clocking
Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) reference clocks and genlock signals to video encoder/decoder FPGAs in 4K/8K broadcast equipment. IC Role / Device Role / Timing Role: High-precision frequency translator converting studio master sync (27 MHz) to multiple video domain frequencies (74.25 MHz, 148.5 MHz, etc.). Use Value: Achieves <10 ps cycle-cycle jitter and ±20 ps phase step resolution-critical for frame-accurate genlock and minimal video artifacts.	Use Scenario: Supplying 500 MHz LVPECL clocks to high-end FPGA transceivers and 100 MHz CMOS clocks to ARM-based SoCs in embedded vision systems. IC Role / Device Role / Timing Role: Configurable quad clock source supporting heterogeneous processor/FPGA timing requirements with independent voltage and format control. Use Value: Eliminates manual clock tree design; programmable phase offset aligns FPGA transceiver sampling edges with SoC processing windows, improving setup/hold margins.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: Providing synchronized 100 MHz HCSL clocks to multiple PCIe Gen 4 switch ASICs in a data center fabric.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter reference clocks with matched phase alignment.

Use Value: Enables full Gen 4 lane compliance (≤0.45 ps RMS jitter) and eliminates need for four discrete oscillators, reducing BOM count and layout area by 60%.

Use Scenario: Generating 125 MHz LVDS clocks for 10 GbE PHYs and 156.25 MHz CMOS clocks for packet processors in enterprise switches.

IC Role / Device Role / Timing Role: Any-frequency clock converter supporting mixed-signal domain bridging between Ethernet MACs, PHYs, and control logic.

Use Value: Single-device solution replaces multiple oscillators and level translators; independent VDDO per output allows direct 1.8 V/2.5 V/3.3 V interface without external buffers.

Broadcast Video Timing

Processor & FPGA Clocking

Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) reference clocks and genlock signals to video encoder/decoder FPGAs in 4K/8K broadcast equipment.

IC Role / Device Role / Timing Role: High-precision frequency translator converting studio master sync (27 MHz) to multiple video domain frequencies (74.25 MHz, 148.5 MHz, etc.).

Use Value: Achieves <10 ps cycle-cycle jitter and ±20 ps phase step resolution-critical for frame-accurate genlock and minimal video artifacts.

Use Scenario: Supplying 500 MHz LVPECL clocks to high-end FPGA transceivers and 100 MHz CMOS clocks to ARM-based SoCs in embedded vision systems.

IC Role / Device Role / Timing Role: Configurable quad clock source supporting heterogeneous processor/FPGA timing requirements with independent voltage and format control.

Use Value: Eliminates manual clock tree design; programmable phase offset aligns FPGA transceiver sampling edges with SoC processing windows, improving setup/hold margins.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05289-GM	Higher integration: integrated crystal, lower jitter (0.35 ps RMS), but fixed 4-output LVDS-only; no HCSL/LVPECL support.	Limited to LVDS-only systems; unsuitable for PCIe Gen 4 HCSL or legacy LVPECL interfaces.	Select when crystal integration and ultra-low jitter are prioritized over output format flexibility.
ICS8430I-01T	Non-programmable, fixed-frequency quad LVDS generator; no I²C interface or frequency synthesis capability.	Only supports pre-defined frequencies (e.g., 100/125/156.25 MHz); no dynamic tuning or spread spectrum.	Select for cost-sensitive, static-clock applications where programmability is unnecessary.

Compared with Si5332A-D05289-GM and ICS8430I-01T, SI5338Q-B05298-GMR uniquely balances full I²C programmability, multi-format output support (LVPECL/LVDS/HCSL/CMOS), PCIe Gen 4 compliance, and field-upgradable configuration-making it optimal for evolving high-speed serial interface designs requiring flexibility and future-proofing.

Availability

SI5338Q-B05298-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching infrastructure, broadcast video synchronization, and FPGA/processor clocking requiring stable component supply across extended product lifecycles.

Supply support for SI5338Q-B05298-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 family is designed as a programmable any-frequency quad clock generator targeting high-speed serial interface timing-including PCIe, Ethernet, Fibre Channel, and broadcast video-where low jitter, flexible output configuration, and software-defined frequency agility are essential.

FAQ

What is the maximum output frequency supported by SI5338Q-B05298-GMR?

The SI5338Q-B05298-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS outputs. For frequencies above 350 MHz, only two unique outputs may operate simultaneously at Fvco/4 and Fvco/6 due to VCO constraints. All outputs maintain 0.7 ps RMS typical jitter within their respective rated ranges.

Does SI5338Q-B05298-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338Q-B05298-GMR meets PCIe Gen 4 Common Clock jitter specifications with ≤0.45 ps RMS (10 kHz–50 MHz) when configured for 100 MHz HCSL outputs. This compliance is verified per PCI-Express Base Specification 4.0 rev. 0.5 using the Skyworks PCIe Clock Jitter Tool and Intel Clock Jitter Tool v1.6.4.

How is SI5338Q-B05298-GMR programmed, and what tools are required?

SI5338Q-B05298-GMR is programmed via its I²C/SMBus-compatible interface using Skyworks' ClockBuilder Pro software. The tool auto-generates configuration files, validates settings against electrical constraints, and supports one-click programming of OTP memory. No external hardware programmer is needed-standard I²C host controllers or evaluation boards suffice.

Can SI5338Q-B05298-GMR generate different output voltages on each channel?

Yes, SI5338Q-B05298-GMR supports independent output supply voltages per driver bank (VDDO0–VDDO3), ranging from 1.4 V to 3.63 V. This enables simultaneous interfacing with 1.8 V FPGAs, 2.5 V ASICs, and 3.3 V legacy logic-all from a single SI5338Q-B05298-GMR device without external level shifters.

What alarm functions does SI5338Q-B05298-GMR provide?

SI5338Q-B05298-GMR provides loss-of-lock (LOL) and loss-of-signal (LOS) detection with dedicated status reporting via the open-drain INTR pin. LOL detection activates within 5–10 ms of PLL unlock; LOS triggers within 2.6–5 µs of input clock dropout. Both alarms are latched and readable via I²C register polling.

SI5338Q-B05298-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338Q-B05298-GMR FAQ

1.How can I place an order for SI5338Q-B05298-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338Q-B05298-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338Q-B05298-GMR reliable?

The price and inventory of SI5338Q-B05298-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338Q-B05298-GMR is usually 5 days.

3.What payment methods are accepted for SI5338Q-B05298-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338Q-B05298-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338Q-B05298-GMR?

SI5338Q-B05298-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338Q-B05298-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338Q-B05298-GMR?

For technical support, including SI5338Q-B05298-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338Q-B05298-GMR requirements.

6.How does Aetrix verify that SI5338Q-B05298-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338Q-B05298-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338Q-B05298-GMR meets industry standards.

7.What is the process for return or replacement of SI5338Q-B05298-GMR?

All SI5338Q-B05298-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338Q-B05298-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338Q-B05298-GMR part is unused and in its original packaging.

Return procedure for SI5338Q-B05298-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…