Skyworks Solutions Inc. SI5338Q-B05389-GMR
- Part No.:
- SI5338Q-B05389-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5338Q-B05389-GMR.pdf
- Description:
- I2C CONTROL, 4-OUTPUT, ANY FREQU
- Quantity:
- Payment:

- Shipping:

Inventory:3,446
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Product details
Overview
SI5338Q-B05389-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and MultiSynth™ frequency synthesis supporting any output frequency from 0.16 MHz to 710 MHz. It replaces up to four crystal oscillators in high-speed serial interface timing applications.
For engineers reviewing the SI5338Q-B05389-GMR datasheet, SI5338Q-B05389-GMR pinout, SI5338Q-B05389-GMR application, or SI5338Q-B05389-GMR equivalent, key selection considerations include its 24-QFN package, independent per-output voltage (1.5/1.8/2.5/3.3 V), spread-spectrum capability (0.5–5.0% down-spread), and I²C/SMBus programmability with ClockBuilder Pro support.
Technical Context
The SI5338Q-B05389-GMR implements a two-stage PLL architecture: a high-stability reference stage followed by four independent MultiSynth™ fractional-N synthesis blocks, each driving a configurable output buffer. Its input flexibility supports crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and differential (5–710 MHz) references.
Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent voltage selection (1.5–3.3 V), programmable phase offset (±45 ns, <20 ps step), and glitchless frequency increment/decrement (1 ppm steps). Loss-of-lock and loss-of-signal alarms are integrated for system monitoring.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Jitter (RMS) | 0.7 ps - meets PCIe Gen 3/4 common clock and SRNS requirements at 100 MHz HCSL output |
| Output Frequency Range | 0.16–710 MHz - covers PCIe, Ethernet, Fibre Channel, and processor/FPGA clocking needs |
| Input Reference Support | Crystal (8–30 MHz), CMOS (5–200 MHz), differential (5–710 MHz) - enables flexible system clock sourcing |
| Output Formats | LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL - supports mixed-signal board-level timing interfaces |
| Supply Voltages | VDD = 1.8/2.5/3.3 V; VDDOx = 1.5/1.8/2.5/3.3 V - allows coexistence with diverse logic families |
| Package | 24-pin QFN, 4 × 4 mm - space-efficient for dense PCB layouts with thermal pad for dissipation |
| Operating Temperature | –40 °C to +85 °C - qualified for industrial and telecom line card environments |
Pinout & Package
The SI5338Q-B05389-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad (RoHS-compliant, GMR suffix). Pin 1 is top-left corner adjacent to notch/dot marking; pin numbering proceeds counterclockwise.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1, IN2, IN5, IN6 | Differential input pairs | Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination |
| IN3, IN4 | Single-ended input pins | Support 5–200 MHz CMOS inputs; VIH/VIL thresholds scale with VDD |
| CLK0A–CLK3B | Differential output pairs (4 channels) | Configurable as LVPECL/LVDS/HCSL/CML; each pair shares VDDOx supply rail |
| VDDO0–VDDO3 | Independent output buffer supplies | Enable per-channel voltage setting (1.5/1.8/2.5/3.3 V) for mixed-voltage system interfacing |
| VDD | Core supply | Accepts 1.8 V (±5%), 2.5 V (±10%), or 3.3 V (±10%) with 45 mA typical current draw |
| SCL, SDA | I²C/SMBus interface | Standard 100/400 kHz operation; supports ClockBuilder Pro configuration and runtime reprogramming |
| INTR | Interrupt output | Open-drain status signal indicating loss-of-lock or loss-of-signal events |
| RSVD_GND | Reserved ground | Internal tie to die substrate; must be connected to PCB ground plane for EMI control |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth™ synthesis | Four independent fractional-N synthesizers enabling true zero-ppm accuracy on all outputs simultaneously |
| PCIe Gen 4 compliance | 0.15–0.45 ps RMS jitter in common-clock mode meets PCIe Base Spec 4.0 rev 0.5 requirements |
| Spread-spectrum modulation | Programmable down-spread (0.5–5.0%) and modulation rate (33–63 kHz) reduces EMI in noise-sensitive systems |
| Glitchless frequency tuning | Pin- or I²C-controlled frequency increment/decrement in 1 ppm steps without output interruption |
| Per-output phase adjustment | ±45 ns range with <20 ps resolution enables precise skew management across multi-lane interfaces |
| External feedback mode | Supports zero-delay operation for clock distribution networks requiring minimal propagation latency |
Applications
| PCIe Gen 4 Switch Timing | Ethernet Switch/Routing |
|---|---|
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 switch ICs in a data center fabric card. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter HCSL clocks with matched phase alignment. Use Value: Enables full Gen 4 lane compliance (≤0.45 ps RMS jitter) while eliminating discrete oscillator count and reducing board area by 75%. | Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, packet processors, and SerDes in enterprise switches. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant frequencies from a single 25 MHz crystal reference. Use Value: Eliminates need for multiple crystals or fixed-ratio PLLs, simplifying BOM and enabling dynamic frequency reconfiguration via I²C. |
| Broadcast Video Timing | FPGA/Processor Clocking |
Use Scenario: Delivering SMPTE ST 2082 (27 Gbps) and ST 2081 (12 Gbps) reference clocks to video encoder/decoder ASICs in broadcast infrastructure. IC Role / Device Role / Timing Role: High-frequency clock generator supporting 270 MHz, 540 MHz, and 710 MHz outputs with sub-ps jitter performance. Use Value: Meets SMPTE jitter masks (e.g., ≤1.0 ps RMS for 12G-SDI) using LVPECL outputs, avoiding costly jitter cleaners. | Use Scenario: Supplying core, DDR, and peripheral clocks to Xilinx Versal or Intel Agilex FPGAs in adaptive compute platforms. IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage rails (1.8 V for I/O, 1.2 V-compatible via level-shifting) and programmable phase offsets. Use Value: Reduces FPGA pin count and routing complexity by integrating multiple clock domains into one device with deterministic skew control. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D05389-GM | Higher integration: includes integrated crystal, lower jitter (0.35 ps RMS), supports up to 10 outputs, but larger 32-QFN package | Preferred for space-constrained designs where crystal omission and ultra-low jitter are critical (e.g., 5G baseband) | Select when crystal integration and sub-0.4 ps jitter outweigh cost and footprint penalties |
| ICS853S02AG-01T | Fixed-frequency dual-output LVDS generator (no I²C, no frequency synthesis), 1.2 ps RMS jitter, 16-TSSOP package | Limited to pre-defined frequencies; suitable only for static clock trees without reconfiguration needs | Choose only for legacy designs requiring pin-compatible drop-in replacement with no firmware changes |
Compared with Si5332A-D05389-GM and ICS853S02AG-01T, the SI5338Q-B05389-GMR uniquely balances programmability, jitter performance, and compact 4×4 mm footprint-making it optimal for PCIe Gen 4, multi-rate Ethernet, and FPGA timing where field-upgradable frequency agility is required without crystal bill-of-materials overhead.
Availability
SI5338Q-B05389-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch timing, Ethernet switching/routing, broadcast video timing, and FPGA/processor clocking requiring stable component supply across production lifecycles.
Supply support for SI5338Q-B05389-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.
The Si5338 product line was engineered for high-performance, software-configurable clock generation in data-intensive systems-specifically targeting PCIe, Ethernet, and broadcast video applications demanding low jitter, multi-format outputs, and field-reprogrammability.
FAQ
What is the maximum differential input frequency supported by the SI5338Q-B05389-GMR?
The SI5338Q-B05389-GMR supports differential input frequencies up to 710 MHz on pins IN1/IN2 and IN5/IN6. This capability enables direct use of high-speed SerDes reference clocks without external division, preserving jitter integrity for PCIe Gen 4 and 25G+ Ethernet applications. The device maintains 0.7 ps RMS jitter performance under these conditions when using low-noise differential sources.
Does the SI5338Q-B05389-GMR support spread-spectrum clocking (SSC), and what are its programmable ranges?
Yes, the SI5338Q-B05389-GMR supports fully programmable spread-spectrum clocking on any output. It offers spread deviation from 0.5% to 5.0%, modulation rates from 33 kHz to 63 kHz, and supports both down-spread and center-spread profiles. These parameters are configured per-output via I²C registers and validated in the ClockBuilder Pro software, enabling EMI reduction without compromising timing margin.
Can the SI5338Q-B05389-GMR generate four different output frequencies simultaneously, and what is the minimum frequency step size?
Yes, the SI5338Q-B05389-GMR can synthesize four independent output frequencies simultaneously using its four MultiSynth™ engines. Each output achieves true zero-ppm accuracy with synthesis resolution down to 1 ppb. Frequency increments/decrements are adjustable in precise 1 ppm steps via pin control or I²C, enabling glitchless real-time tuning for dynamic system requirements.
What output voltage levels does the SI5338Q-B05389-GMR support per channel, and how is this configured?
The SI5338Q-B05389-GMR supports independent output supply voltages of 1.5 V, 1.8 V, 2.5 V, or 3.3 V per channel via dedicated VDDO0–VDDO3 pins. Each voltage rail powers its corresponding CLKxA/CLKxB pair and is set externally-no internal regulation. This enables direct interfacing with mixed-voltage components (e.g., 1.8 V FPGA I/O banks and 3.3 V legacy peripherals) without level shifters.
Is ClockBuilder Pro software required to configure the SI5338Q-B05389-GMR, or can it be programmed in-system via I²C?
ClockBuilder Pro is optional for initial design and validation but not required for in-system operation. The SI5338Q-B05389-GMR supports full I²C/SMBus programming (standard-mode and fast-mode) for runtime configuration, frequency updates, and status monitoring. Pre-programmed OTP versions are also available, allowing boot-time clock readiness without host intervention.
SI5338Q-B05389-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5338Q-B05389-GMR FAQ
1.How can I place an order for SI5338Q-B05389-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5338Q-B05389-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5338Q-B05389-GMR reliable?
The price and inventory of SI5338Q-B05389-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338Q-B05389-GMR is usually 5 days.
3.What payment methods are accepted for SI5338Q-B05389-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338Q-B05389-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5338Q-B05389-GMR?
SI5338Q-B05389-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5338Q-B05389-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5338Q-B05389-GMR?
For technical support, including SI5338Q-B05389-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338Q-B05389-GMR requirements.
6.How does Aetrix verify that SI5338Q-B05389-GMR is sourced from the original manufacturer or authorized distributors?
All SI5338Q-B05389-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338Q-B05389-GMR meets industry standards.
7.What is the process for return or replacement of SI5338Q-B05389-GMR?
All SI5338Q-B05389-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338Q-B05389-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5338Q-B05389-GMR part is unused and in its original packaging.
Return procedure for SI5338Q-B05389-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5338Q-B05389-GMR Tags

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