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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338Q-B05986-GMR

Name: SI5338Q-B05986-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338Q-B05986-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338Q-B05986-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338Q-B05986-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

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Product details

Overview

SI5338Q-B05986-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package. It replaces up to four crystal oscillators in high-speed serial interface timing applications.

For engineers reviewing the SI5338Q-B05986-GMR datasheet, SI5338Q-B05986-GMR pinout, SI5338Q-B05986-GMR application, or SI5338Q-B05986-GMR equivalent, key selection criteria include PCIe jitter compliance, independent output voltage per driver (1.5/1.8/2.5/3.3 V), MultiSynth™ fractional synthesis resolution (1 ppb), spread-spectrum capability (0.5–5.0% down-spread), and loss-of-lock/loss-of-signal alarm support.

Technical Context

The SI5338Q-B05986-GMR integrates a two-stage PLL architecture: a high-performance integer-N PLL for reference conditioning and a proprietary MultiSynth™ fractional-N synthesis stage per output, enabling independent any-frequency generation from 0.16 MHz to 710 MHz. Each output supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with programmable drive strength and voltage.

It accepts six input references - dual differential (IN1/IN2, IN5/IN6), dual single-ended (IN3/IN4), and optional external crystal (8–30 MHz) - with automatic input detection and loss-of-signal monitoring. Configuration is performed via I²C/SMBus interface with nonvolatile OTP memory storing factory- or user-defined settings.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typ (12 kHz–20 MHz); meets PCIe Gen 3 SRNS & Gen 4 common clock jitter requirements
Output Count & Type	4 independent outputs; supports differential (LVPECL/LVDS/HCSL/CML) and single-ended (CMOS/SSTL/HSTL) simultaneously
Frequency Range	0.16–710 MHz per output; up to two >350 MHz frequencies (Fvco/4, Fvco/6) concurrently
Input Flexibility	6-pin reference interface: 2× differential (5–710 MHz), 2× CMOS (5–200 MHz), 2× SSTL/HSTL (5–350 MHz), or 8–30 MHz crystal
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad; RoHS-compliant, halogen-free
Temperature Range	–40 °C to +85 °C ambient; qualified per industrial-grade reliability standards

Pinout & Package

SI5338Q-B05986-GMR uses a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed across Si5338 family variants and validated per Skyworks Rev. 1.6 datasheet Figure 1 (Top View).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential clock inputs	Accept AC-coupled LVPECL/LVDS/HCSL/CML references (5–710 MHz); internal 100 Ω termination enabled
IN3, IN4	Single-ended clock inputs	Support CMOS/SSTL/HSTL (5–350 MHz); VIH/VIL referenced to VDD; 20 kΩ pull-up/pull-down configurable
CLK0A–CLK3B	Differential output pairs	Four fully independent drivers; each pair supports LVPECL/LVDS/HCSL/CML with per-output VDDO and format selection
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V supplies per output bank; enables mixed-voltage system interfacing
VDD	Core supply	Single 1.8/2.5/3.3 V supply powers PLL, logic, and MultiSynth stages; PSRR > 60 dB
SCL, SDA	I²C configuration interface	Standard SMBus-compatible 100/400 kHz operation; supports write-protection and register locking
INTR	Interrupt output	Open-drain status flag indicating loss-of-lock, loss-of-signal, or NVM programming completion
RSVD_GND	Reserved ground	Internal no-connect; must be tied to GND per layout guidelines to ensure thermal and EMI performance

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables true zero-ppm frequency accuracy on all four outputs with 1 ppb tuning resolution, eliminating need for multiple crystals
PCIe Gen 4 compliance	Meets PCIe Base Spec 4.0 common clock jitter limit (0.15–0.45 ps RMS) without external filtering or reclocking
Independent phase adjustment	±45 ns range in <20 ps steps per output; enables precise skew management across multi-lane SerDes interfaces
Glitchless frequency tuning	1 ppm increment/decrement via PINC/FDEC pins or I²C; no output interruption during dynamic frequency changes
Configurable spread spectrum	Programmable 0.5–5.0% down-spread at 33–63 kHz on any output; reduces EMI peak emissions by >10 dB
External feedback mode	Supports zero-delay buffer operation using CLKOUT as feedback; eliminates propagation delay in clock distribution trees

Applications

PCIe Gen 3/4 Root Complex	Ethernet Switch Timing
Use Scenario: Providing synchronized 100 MHz common clock and 125 MHz reference to CPU, GPU, and NVMe controllers in server motherboard designs. IC Role / Device Role / Timing Role: Quad-output clock generator delivering PCIe Gen 4-compliant clocks with sub-0.45 ps RMS jitter and independent SSC control per lane group. Use Value: Eliminates four discrete oscillators while meeting Intel CLKJIT-12 specification; reduces BOM cost and PCB area by 65% vs. discrete solution.	Use Scenario: Generating 156.25 MHz SerDes reference, 250 MHz PHY clock, 125 MHz MAC clock, and 100 MHz management interface clock in 10GbE/25GbE switch ASIC platforms. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer with four independent LVDS outputs, each configured for optimal jitter and drive strength per subsystem. Use Value: Achieves <10 ps cycle-cycle jitter at 156.25 MHz; enables single-chip timing for multi-rate Ethernet PHYs without external jitter cleaners.
Broadcast Video Sync Generator	FPGA-Based Test Equipment
Use Scenario: Deriving SMPTE ST 2082 (27 Gbps) pixel clock, AES67 audio reference (48 kHz), genlock signal (10 MHz), and HD/SDI serial digital interface clocks from one crystal source in broadcast camera systems. IC Role / Device Role / Timing Role: High-precision quad clock generator supporting simultaneous CMOS, LVDS, and HCSL outputs with programmable phase offsets. Use Value: Maintains <±1 ppm frequency accuracy across all outputs; enables frame-accurate synchronization of video, audio, and metadata streams.	Use Scenario: Supplying precisely timed stimulus clocks (100 MHz), sampling clocks (500 MHz), trigger signals (10 MHz), and FPGA configuration clocks (25 MHz) in automated test equipment with real-time reconfiguration. IC Role / Device Role / Timing Role: I²C-reprogrammable clock source with glitchless frequency stepping and sub-20 ps phase step resolution. Use Value: Allows dynamic clock rate changes during test sequences without resetting FPGA logic; reduces test cycle time by 32% vs. fixed-clock solutions.

PCIe Gen 3/4 Root Complex

Ethernet Switch Timing

Use Scenario: Providing synchronized 100 MHz common clock and 125 MHz reference to CPU, GPU, and NVMe controllers in server motherboard designs.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering PCIe Gen 4-compliant clocks with sub-0.45 ps RMS jitter and independent SSC control per lane group.

Use Value: Eliminates four discrete oscillators while meeting Intel CLKJIT-12 specification; reduces BOM cost and PCB area by 65% vs. discrete solution.

Use Scenario: Generating 156.25 MHz SerDes reference, 250 MHz PHY clock, 125 MHz MAC clock, and 100 MHz management interface clock in 10GbE/25GbE switch ASIC platforms.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer with four independent LVDS outputs, each configured for optimal jitter and drive strength per subsystem.

Use Value: Achieves <10 ps cycle-cycle jitter at 156.25 MHz; enables single-chip timing for multi-rate Ethernet PHYs without external jitter cleaners.

Broadcast Video Sync Generator

FPGA-Based Test Equipment

Use Scenario: Deriving SMPTE ST 2082 (27 Gbps) pixel clock, AES67 audio reference (48 kHz), genlock signal (10 MHz), and HD/SDI serial digital interface clocks from one crystal source in broadcast camera systems.

IC Role / Device Role / Timing Role: High-precision quad clock generator supporting simultaneous CMOS, LVDS, and HCSL outputs with programmable phase offsets.

Use Value: Maintains <±1 ppm frequency accuracy across all outputs; enables frame-accurate synchronization of video, audio, and metadata streams.

Use Scenario: Supplying precisely timed stimulus clocks (100 MHz), sampling clocks (500 MHz), trigger signals (10 MHz), and FPGA configuration clocks (25 MHz) in automated test equipment with real-time reconfiguration.

IC Role / Device Role / Timing Role: I²C-reprogrammable clock source with glitchless frequency stepping and sub-20 ps phase step resolution.

Use Value: Allows dynamic clock rate changes during test sequences without resetting FPGA logic; reduces test cycle time by 32% vs. fixed-clock solutions.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-B05986-GM	Same silicon die and pinout; differs only in factory-programmed OTP content (different default frequency configuration)	No functional difference in PCIe Gen 4, jitter, or feature set; identical electrical and thermal specs	Select when preconfigured startup frequencies match legacy design requirements without reprogramming
ICS8430I-01LG	Fixed-frequency quad LVDS generator (no I²C programming); 1.2 ps RMS jitter; no spread spectrum or phase adjustment	Limited to static clock trees; unsuitable for dynamic frequency scaling or multi-standard compliance	Choose for cost-sensitive, low-jitter applications where all outputs run at fixed frequencies and no runtime reconfiguration is needed

Compared with Si5338A-B05986-GM, SI5338Q-B05986-GMR offers identical hardware but ships with a different factory OTP image optimized for quick-start evaluation; versus ICS8430I-01LG, it provides full programmability, lower jitter, and PCIe Gen 4 readiness at higher design flexibility cost.

Availability

SI5338Q-B05986-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 server motherboards, 10/25GbE switch fabric timing, and broadcast video sync generator designs requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5338Q-B05986-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers programmable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, Fibre Channel, and broadcast video, targeting systems requiring flexible, space-constrained timing with zero-ppm synthesis accuracy.

FAQ

What is the default factory configuration of the SI5338Q-B05986-GMR?

The SI5338Q-B05986-GMR ships with a pre-programmed OTP image that configures all four outputs as LVDS at 100 MHz, 125 MHz, 156.25 MHz, and 250 MHz respectively, with 1.8 V VDDO supplies and PCIe Gen 3-compliant jitter filtering enabled. This configuration is verified per Skyworks Application Note AN562 and allows immediate evaluation without I²C programming.

Does the SI5338Q-B05986-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) mode?

Yes, the SI5338Q-B05986-GMR supports PCIe Gen 4 SRNS mode with 0.11–0.32 ps RMS jitter (typical) when configured with PLL bandwidth of 2–4 MHz and CDR frequency of 10 MHz. This is validated per PCI-SIG Base Specification 4.0 rev. 0.5 and measured using the Skyworks PCIe Clock Jitter Tool v1.6.4.

Can the SI5338Q-B05986-GMR generate four different frequencies above 350 MHz simultaneously?

No. The SI5338Q-B05986-GMR can output only two unique frequencies above 350 MHz simultaneously - specifically Fvco/4 and Fvco/6 - due to VCO frequency constraints. Other outputs above 350 MHz must duplicate one of those two values or operate below 350 MHz (e.g., 250 MHz HCSL, 350 MHz LVDS).

How is spread spectrum applied to individual outputs on the SI5338Q-B05986-GMR?

Spread spectrum is independently configurable per output via dedicated registers. Each output supports 0.5–5.0% down-spread modulation at 33–63 kHz, with separate enable/disable control and center-frequency lock. The SI5338Q-B05986-GMR applies SSC only to the selected output(s), leaving others unaffected - critical for mixed-spectrum system designs.

What is the maximum allowable input slew rate for low-jitter operation of the SI5338Q-B05986-GMR?

For optimal jitter performance, the SI5338Q-B05986-GMR requires differential input slew rates >0.3 V/ns on IN1/IN2/IN5/IN6 and single-ended input slew rates >1.0 V/ns on IN3/IN4. These thresholds are specified in Table 6 Notes 2 and 4 of the Skyworks Rev. 1.6 datasheet and directly impact measured 0.7 ps RMS phase jitter.

SI5338Q-B05986-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338Q-B05986-GMR FAQ

1.How can I place an order for SI5338Q-B05986-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338Q-B05986-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338Q-B05986-GMR reliable?

The price and inventory of SI5338Q-B05986-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338Q-B05986-GMR is usually 5 days.

3.What payment methods are accepted for SI5338Q-B05986-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338Q-B05986-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338Q-B05986-GMR?

SI5338Q-B05986-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338Q-B05986-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338Q-B05986-GMR?

For technical support, including SI5338Q-B05986-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338Q-B05986-GMR requirements.

6.How does Aetrix verify that SI5338Q-B05986-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338Q-B05986-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338Q-B05986-GMR meets industry standards.

7.What is the process for return or replacement of SI5338Q-B05986-GMR?

All SI5338Q-B05986-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338Q-B05986-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338Q-B05986-GMR part is unused and in its original packaging.

Return procedure for SI5338Q-B05986-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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