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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338Q-B06140-GMR

Name: SI5338Q-B06140-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338Q-B06140-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338Q-B06140-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338Q-B06140-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338Q-B06140-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis with 0 ppm precision per output, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL outputs up to 710 MHz. It replaces up to four discrete oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA-based compute platforms.

For engineers reviewing the SI5338Q-B06140-GMR datasheet, SI5338Q-B06140-GMR pinout, SI5338Q-B06140-GMR application, or SI5338Q-B06140-GMR equivalent, key selection criteria include differential output jitter performance at 125 MHz (0.7 ps RMS), independent per-output voltage configuration (1.5/1.8/2.5/3.3 V), spread-spectrum modulation capability (0.5–5.0% down-spread), and 24-pin 4×4 mm QFN package compatibility with PCIe Gen 4 reference clock requirements.

Technical Context

The SI5338Q-B06140-GMR integrates a dual-stage PLL architecture: a high-stability input stage locking to external crystal (8–30 MHz) or differential/CMOS references (5–710 MHz), followed by four independent MultiSynth™ fractional-N synthesizers enabling any-frequency generation on each of four differential output drivers. Each synthesizer supports integer/fractional mode operation with programmable initial phase offset (±45 ns) and glitchless frequency increment/decrement in 1 ppm steps.

Its output stage provides per-driver configurability for signal format (LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL), output supply voltage (VDDOx = 1.4–3.63 V), and spread-spectrum parameters (modulation rate 33–63 kHz, spread 0.5–5.0%). Loss-of-lock and loss-of-signal monitoring, I²C/SMBus interface, and OTP NVM for factory programming are integrated.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements
Output Frequency Range	0.16–710 MHz per channel; supports simultaneous dual >350 MHz outputs (Fvco/4 & Fvco/6)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Output Formats	LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL - each independently configurable per driver
Supply Voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: 1.5/1.8/2.5/3.3 V selectable per driver
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; RoHS-compliant, halogen-free
Operating Temperature	–40 °C to +85 °C ambient; qualified for industrial and telecom line card environments

Pinout & Package

SI5338Q-B06140-GMR uses a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin 1 is top-left corner (IN1), pin 24 is bottom-right (GND). The package supports reflow soldering per JEDEC J-STD-020 (peak 260 °C).

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential Input Pairs	Accept AC-coupled differential clocks (5–710 MHz); require external 100 Ω termination
IN3, IN4	Single-Ended Inputs	Support CMOS/SSTL/HSTL references (5–350 MHz); VIH/VIL referenced to VDD
CLK0A–CLK3B	Differential Output Pairs	Four independent LVPECL/LVDS/HCSL/CML outputs; each pair shares VDDOx supply
VDDO0–VDDO3	Output Buffer Supplies	Independent 1.4–3.63 V supplies per output bank; enable mixed-voltage system interfacing
VDD	Core Supply	Single 1.8/2.5/3.3 V core rail; PSRR optimized for low-noise clock generation
SCL, SDA	I²C Interface	Standard SMBus-compatible 2-wire bus (up to 400 kHz); supports factory and field programming
INTR	Interrupt Output	Open-drain status indicator for loss-of-lock and loss-of-signal events

Key Features

Feature	Design Value
MultiSynth™ Synthesis	Four independent fractional-N synthesizers deliver true zero-ppm accuracy on all outputs without external loop filters
PCIe Compliance	Fully compliant with PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS specifications; validated using Intel Clock Jitter Tool
Per-Output Flexibility	Each of four output drivers supports independent format, voltage, frequency, phase offset (±45 ns), and spread-spectrum settings
Low-Power Operation	45 mA typical core current at 100 MHz on all outputs; <12 mA in buffer-only (PLL bypass) mode
Configurable Spread Spectrum	Programmable down-spread (0.5–5.0%), modulation rate (33–63 kHz), and center frequency for EMI reduction

Applications

PCIe Gen 4 Root Complex Timing	Ethernet Switch Clocking
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 endpoints and switch fabric in a 1U server motherboard. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant reference clocks with matched skew (<100 ps) and SRNS compliance. Use Value: Eliminates need for four discrete oscillators; enables single-point jitter control and dynamic frequency margining via I²C.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 10GbE/25GbE PHYs and packet processor interfaces in a modular switch ASIC design. IC Role / Device Role / Timing Role: Any-frequency synthesizer providing three distinct high-speed clocks from one crystal reference, with independent LVDS and HCSL outputs. Use Value: Reduces BOM count and layout area; supports multi-rate Ethernet PHYs without external dividers or translators.
FPGA-Based Video Processing	Telecom Line Card Synchronization
Use Scenario: Delivering pixel clock (148.5 MHz), DDR memory clock (400 MHz), and AXI interconnect clock (200 MHz) to an FPGA-based broadcast video encoder board. IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed-signal formats (LVDS for pixel clock, HSTL for DDR, CMOS for logic) from a single 25 MHz crystal. Use Value: Enables precise phase alignment across domains; eliminates timing closure issues caused by multiple oscillator sources.	Use Scenario: Generating E1/T1 framing clocks (2.048 MHz, 1.544 MHz), SerDes reference (156.25 MHz), and processor clocks (100 MHz) in a carrier-grade SDH/SONET line card. IC Role / Device Role / Timing Role: High-reliability clock generator with loss-of-signal detection and wide temperature range (–40 to +85 °C) for telecom infrastructure. Use Value: Meets GR-1244-CORE jitter requirements; supports hot-swap and redundancy via I²C-configurable failover behavior.

PCIe Gen 4 Root Complex Timing

Ethernet Switch Clocking

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen 4 endpoints and switch fabric in a 1U server motherboard.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant reference clocks with matched skew (<100 ps) and SRNS compliance.

Use Value: Eliminates need for four discrete oscillators; enables single-point jitter control and dynamic frequency margining via I²C.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 10GbE/25GbE PHYs and packet processor interfaces in a modular switch ASIC design.

IC Role / Device Role / Timing Role: Any-frequency synthesizer providing three distinct high-speed clocks from one crystal reference, with independent LVDS and HCSL outputs.

Use Value: Reduces BOM count and layout area; supports multi-rate Ethernet PHYs without external dividers or translators.

FPGA-Based Video Processing

Telecom Line Card Synchronization

Use Scenario: Delivering pixel clock (148.5 MHz), DDR memory clock (400 MHz), and AXI interconnect clock (200 MHz) to an FPGA-based broadcast video encoder board.

IC Role / Device Role / Timing Role: Configurable quad clock source supporting mixed-signal formats (LVDS for pixel clock, HSTL for DDR, CMOS for logic) from a single 25 MHz crystal.

Use Value: Enables precise phase alignment across domains; eliminates timing closure issues caused by multiple oscillator sources.

Use Scenario: Generating E1/T1 framing clocks (2.048 MHz, 1.544 MHz), SerDes reference (156.25 MHz), and processor clocks (100 MHz) in a carrier-grade SDH/SONET line card.

IC Role / Device Role / Timing Role: High-reliability clock generator with loss-of-signal detection and wide temperature range (–40 to +85 °C) for telecom infrastructure.

Use Value: Meets GR-1244-CORE jitter requirements; supports hot-swap and redundancy via I²C-configurable failover behavior.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06140-GM	Higher integration: 8 outputs, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency; requires different programming flow	Better suited for JESD204B ADC/DAC synchronization and multi-channel RF systems requiring sub-100 fs jitter	Select when >4 outputs or ultra-low jitter (<0.4 ps RMS) is required; not drop-in compatible due to pinout and register map differences
ICS853S01AGI-01LFT	Fixed-function 4-output LVDS clock fanout buffer; no frequency synthesis, no I²C, no spread spectrum; 1.2 ps RMS jitter	Limited to fanout-only use cases with fixed input-to-output ratios; no any-frequency generation capability	Choose only for simple clock distribution where input frequency matches all required outputs; lacks SI5338Q-B06140-GMR's synthesis flexibility

Compared with Si5332A-D06140-GM, SI5338Q-B06140-GMR offers broader input reference support and simpler I²C configuration but higher jitter; versus ICS853S01AGI-01LFT, it adds full synthesis and programmability at the cost of higher complexity and power.

Availability

SI5338Q-B06140-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 reference clocking, FPGA-based video processing, and telecom line card synchronization requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5338Q-B06140-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5338 product line delivers highly flexible, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, Fibre Channel, and broadcast video, targeting systems requiring multi-frequency synthesis from a single device.

FAQ

What is the maximum output frequency supported by SI5338Q-B06140-GMR in LVPECL format?

The SI5338Q-B06140-GMR supports LVPECL output frequencies up to 710 MHz. This capability is enabled by its MultiSynth™ architecture and internal VCO operating at up to 3.5 GHz. Operation above 350 MHz is limited to two unique frequencies simultaneously (Fvco/4 and Fvco/6), as specified in the functional description and Table 6 of the datasheet.

Does SI5338Q-B06140-GMR support PCIe Gen 4 Common Clock compliance?

Yes, SI5338Q-B06140-GMR meets PCIe Gen 4 Common Clock jitter requirements with 0.15–0.45 ps RMS (10 kHz–50 MHz) under specified test conditions (100 MHz HCSL outputs, PLL BW 2–4 MHz, CDR = 10 MHz). This compliance is explicitly documented in Table 12 and confirmed using the Skyworks PCIe Clock Jitter Tool.

Can SI5338Q-B06140-GMR generate different output voltages on each driver?

Yes, SI5338Q-B06140-GMR supports independent output supply voltages per driver bank (VDDO0–VDDO3), allowing simultaneous 1.8 V LVDS, 2.5 V HCSL, and 3.3 V CMOS outputs. Each VDDO pin must be decoupled locally, and voltage selection is configured via I²C registers controlling the output buffer biasing.

What input reference types does SI5338Q-B06140-GMR accept?

SI5338Q-B06140-GMR accepts four input reference types: (1) 8–30 MHz fundamental-mode crystals, (2) single-ended CMOS clocks (5–200 MHz), (3) single-ended SSTL/HSTL clocks (5–350 MHz), and (4) differential inputs (5–710 MHz on IN1/IN2 or IN5/IN6 pairs). All inputs support loss-of-signal detection.

Is SI5338Q-B06140-GMR pin-compatible with other Si5338 variants?

Yes, all Si5338 variants-including SI5338Q-B06140-GMR-share the same 24-pin QFN package and pinout. Differences between variants (e.g., Si5338A, Si5338B, Si5338Q) relate to factory-programmed configurations and OTP content, not physical layout or electrical pin functions.

SI5338Q-B06140-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338Q-B06140-GMR FAQ

1.How can I place an order for SI5338Q-B06140-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338Q-B06140-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338Q-B06140-GMR reliable?

The price and inventory of SI5338Q-B06140-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338Q-B06140-GMR is usually 5 days.

3.What payment methods are accepted for SI5338Q-B06140-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338Q-B06140-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338Q-B06140-GMR?

SI5338Q-B06140-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338Q-B06140-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338Q-B06140-GMR?

For technical support, including SI5338Q-B06140-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338Q-B06140-GMR requirements.

6.How does Aetrix verify that SI5338Q-B06140-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338Q-B06140-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338Q-B06140-GMR meets industry standards.

7.What is the process for return or replacement of SI5338Q-B06140-GMR?

All SI5338Q-B06140-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338Q-B06140-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338Q-B06140-GMR part is unused and in its original packaging.

Return procedure for SI5338Q-B06140-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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