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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338Q-B06188-GM

Name: SI5338Q-B06188-GM
Brand: Skyworks Solutions Inc.
SKU: SI5338Q-B06188-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338Q-B06188-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338Q-B06188-GM.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338Q-B06188-GM from Skyworks Solutions is a quad-output, I²C-programmable clock generator with MultiSynth™ frequency synthesis. It delivers four independent, any-frequency clocks (0.16–710 MHz) with 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 and SRNS compliance, and configurable LVPECL/LVDS/HCSL/CMOS outputs. It replaces up to four crystal oscillators in FPGA, processor, and Ethernet switch timing systems.

For engineers reviewing the SI5338Q-B06188-GM datasheet, SI5338Q-B06188-GM pinout, SI5338Q-B06188-GM application, or SI5338Q-B06188-GM equivalent, key selection criteria include differential output jitter performance (0.7 ps RMS), PCIe Gen 4 common-clock compliance, independent per-output voltage control (1.5/1.8/2.5/3.3 V), 24-QFN package footprint, and I²C/SMBus programmability with ClockBuilder Pro support.

Technical Context

The SI5338Q-B06188-GM implements a two-stage PLL architecture: a high-stability reference PLL (Stage 1) locks to an external crystal (8–30 MHz) or clock input (5–710 MHz), followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each synthesizer supports integer or fractional mode with <1 ppb frequency resolution.

Output stage flexibility includes per-driver format selection (LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL), independent VDDO supply per bank (1.5–3.3 V), and hardware- or I²C-controlled phase/frequency increment/decrement (20 ps / 1 ppm steps). Loss-of-signal and loss-of-lock monitoring are integrated with interrupt reporting via INTR pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3/4 SRNS and GbE jitter requirements at 125 MHz and 155.52 MHz
Output Frequency Range	0.16–710 MHz - supports PCIe 100 MHz, Ethernet 125/156.25 MHz, Fibre Channel 1.0625 GHz (via Fvco/4), and custom rates
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - enables flexible system clock sourcing
Output Driver Flexibility	Four differential outputs (CLK0A/B–CLK3A/B) with independent format/voltage - allows mixed-signal interface (e.g., LVDS to FPGA, HCSL to CPU)
Supply Voltages	VDD = 1.8/2.5/3.3 V ±10%; VDDOx = 1.4–3.63 V - supports multi-rail SoC/FPGA power domains
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch - compact footprint compatible with high-density PCB layouts
Operating Temperature	–40 °C to +85 °C - qualified for industrial and telecom line card environments

Pinout & Package

SI5338Q-B06188-GM uses a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin 1 is top-left corner (IN1), pins numbered counterclockwise. Ground and power pins are distributed for low-noise operation; all VDDO pins are independently routed to support mixed-voltage outputs.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential clock inputs	Accept AC-coupled LVPECL/LVDS/CML references up to 710 MHz; require external 100 Ω termination
IN3, IN4	Single-ended clock inputs	Support CMOS/SSTL/HSTL signals (5–350 MHz); internal 20 kΩ pull-up/pull-down configurable
CLK0A–CLK3B	Differential output pairs	Four independent output banks; each pair (e.g., CLK0A/CLK0B) shares VDDO0 and driver format settings
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V rails per output bank - enables mixed-interface clocking without level shifters
SCL, SDA	I²C/SMBus interface	Standard 100 kHz/400 kHz operation; supports ClockBuilder Pro configuration and runtime reprogramming
INTR	Interrupt output	Open-drain status indicator for loss-of-signal (LOS) and loss-of-lock (LOL); active-low assertion

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent fractional-N synthesizers enabling zero-ppm accuracy on any output frequency between 0.16–710 MHz
PCIe Gen 4 Common Clock compliance	0.15–0.45 ps RMS jitter across 10 kHz–50 MHz bandwidth satisfies PCIe Base Spec 4.0 rev 0.5 timing budget
Per-output voltage and format control	Each of four output banks supports independent VDDO (1.5/1.8/2.5/3.3 V) and signal format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL)
Hardware-based frequency tuning	PINC/FDEC pins enable glitchless real-time frequency adjustment in 1 ppm steps without I²C traffic or register writes
Programmable spread spectrum	Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, 5–350 MHz carrier - reduces EMI in dense PCBs
Zero-delay mode support	External feedback path (fb pin) enables synchronous clock distribution with matched input-to-output delay across multiple devices

Applications

PCIe Gen 4 Switch Timing	Ethernet 10GbE PHY Clocking
Use Scenario: High-speed switch ASIC requiring synchronized 100 MHz common clock across multiple PCIe lanes and SerDes blocks. IC Role / Device Role / Timing Role: Quad-output clock generator providing PCIe Gen 4-compliant 100 MHz (HCSL) and auxiliary clocks (e.g., 125 MHz for management interface). Use Value: Meets PCIe Gen 4 SRNS jitter spec (≤0.32 ps RMS) while eliminating four discrete oscillators and reducing BOM count and layout area.	Use Scenario: 10GbE line card with dual PHYs needing precise 156.25 MHz reference and 125 MHz management clock. IC Role / Device Role / Timing Role: Single-chip source for both primary data-rate clock (156.25 MHz LVDS) and secondary control clock (125 MHz CMOS). Use Value: Achieves 0.7 ps RMS jitter at 156.25 MHz, ensuring IEEE 802.3ae compliance; eliminates inter-clock skew between PHYs.
FPGA-Based Broadcast Video System	Telecom Line Card Synchronization
Use Scenario: SMPTE ST 2082-1 video processing platform requiring genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating three exact video rates from a single 25 MHz crystal reference. Use Value: Delivers true zero-ppm accuracy on all outputs using MultiSynth™ integer mode - critical for frame-accurate video sync and lip-sync.	Use Scenario: OTN/SDH line card needing SONET OC-192 (9.953 Gbps) clock recovery and 155.52 MHz system timing. IC Role / Device Role / Timing Role: Low-jitter clock generator producing 155.52 MHz (LVDS) and 125 MHz (HCSL) from a 19.44 MHz OC-12 reference. Use Value: 0.7 ps RMS jitter at 155.52 MHz satisfies ITU-T G.823/G.8262 wander and jitter masks for telecom-grade synchronization.

PCIe Gen 4 Switch Timing

Ethernet 10GbE PHY Clocking

Use Scenario: High-speed switch ASIC requiring synchronized 100 MHz common clock across multiple PCIe lanes and SerDes blocks.

IC Role / Device Role / Timing Role: Quad-output clock generator providing PCIe Gen 4-compliant 100 MHz (HCSL) and auxiliary clocks (e.g., 125 MHz for management interface).

Use Value: Meets PCIe Gen 4 SRNS jitter spec (≤0.32 ps RMS) while eliminating four discrete oscillators and reducing BOM count and layout area.

Use Scenario: 10GbE line card with dual PHYs needing precise 156.25 MHz reference and 125 MHz management clock.

IC Role / Device Role / Timing Role: Single-chip source for both primary data-rate clock (156.25 MHz LVDS) and secondary control clock (125 MHz CMOS).

Use Value: Achieves 0.7 ps RMS jitter at 156.25 MHz, ensuring IEEE 802.3ae compliance; eliminates inter-clock skew between PHYs.

FPGA-Based Broadcast Video System

Telecom Line Card Synchronization

Use Scenario: SMPTE ST 2082-1 video processing platform requiring genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks.

IC Role / Device Role / Timing Role: Any-frequency synthesizer generating three exact video rates from a single 25 MHz crystal reference.

Use Value: Delivers true zero-ppm accuracy on all outputs using MultiSynth™ integer mode - critical for frame-accurate video sync and lip-sync.

Use Scenario: OTN/SDH line card needing SONET OC-192 (9.953 Gbps) clock recovery and 155.52 MHz system timing.

IC Role / Device Role / Timing Role: Low-jitter clock generator producing 155.52 MHz (LVDS) and 125 MHz (HCSL) from a 19.44 MHz OC-12 reference.

Use Value: 0.7 ps RMS jitter at 155.52 MHz satisfies ITU-T G.823/G.8262 wander and jitter masks for telecom-grade synchronization.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06188-GM	Higher integration: 8 outputs, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at high-channel-count ADC/DAC timing and 5G wireless infrastructure	Select when >4 outputs or sub-0.4 ps jitter required; not drop-in due to different pinout and register map
ICS854S01IAGLF	Fixed-function 4-output LVDS generator; no I²C programming; max 700 MHz output; 1.2 ps RMS jitter	Limited to pre-defined frequencies; no spread spectrum or phase adjustment	Choose for cost-sensitive, static-clock applications where programmability is unnecessary

Compared with Si5332A-D06188-GM and ICS854S01IAGLF, the SI5338Q-B06188-GM offers optimal balance of programmability, jitter performance, and pin-compatible scalability within the Si5338 family-enabling firmware-driven clock reconfiguration without hardware changes.

Availability

SI5338Q-B06188-GM is available at Aetrix Electronics and suitable for PCIe Gen 4 switch design, 10GbE PHY timing, and broadcast video equipment requiring stable component supply and long-term production continuity.

Supply support for SI5338Q-B06188-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5338 product line was engineered for high-performance, software-configurable clock generation in multi-protocol systems-enabling consolidation of discrete oscillators and buffers into a single, field-upgradable IC for FPGA, processor, and networking applications.

FAQ

What is the maximum output frequency supported by the SI5338Q-B06188-GM?

The SI5338Q-B06188-GM supports up to 710 MHz on LVPECL/LVDS/CML outputs, 250 MHz on HCSL, and 200 MHz on CMOS. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6) per the device's synthesis architecture. All outputs maintain ≤0.7 ps RMS jitter at rated frequencies when using low-noise differential references.

Does the SI5338Q-B06188-GM support PCIe Gen 4 Common Clock compliance?

Yes, the SI5338Q-B06188-GM is explicitly validated for PCIe Gen 4 Common Clock compliance with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz) under specified conditions (100 MHz HCSL output, PLL BW 2–5 MHz, CDR = 10 MHz). This meets PCI-SIG Base Specification 4.0 rev 0.5 requirements for host and endpoint timing.

How is the SI5338Q-B06188-GM programmed, and what tools are required?

The SI5338Q-B06188-GM is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software. The tool provides GUI-based configuration of all outputs, jitter optimization, spread spectrum settings, and one-click .hex file generation. No external programmer is needed-configuration can be loaded at boot via EEPROM or dynamically during operation.

Can the SI5338Q-B06188-GM generate different output voltages on each channel?

Yes, the SI5338Q-B06188-GM supports independent VDDO supplies (VDDO0–VDDO3) per output bank, allowing simultaneous 1.8 V LVDS, 2.5 V HCSL, and 3.3 V CMOS outputs. Each VDDO pin must be decoupled locally, and voltage selection is configured per-output in the device registers-not hardware-strapped.

What is the function of the INTR pin on the SI5338Q-B06188-GM?

The INTR pin on the SI5338Q-B06188-GM is an open-drain interrupt output that asserts low upon detection of loss-of-signal (LOS) on any enabled input clock or loss-of-lock (LOL) in the PLL. It supports system-level fault monitoring and can trigger MCU interrupts or status LEDs without requiring continuous I²C polling of status registers.

SI5338Q-B06188-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338Q-B06188-GM FAQ

1.How can I place an order for SI5338Q-B06188-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338Q-B06188-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338Q-B06188-GM reliable?

The price and inventory of SI5338Q-B06188-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338Q-B06188-GM is usually 5 days.

3.What payment methods are accepted for SI5338Q-B06188-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338Q-B06188-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338Q-B06188-GM?

SI5338Q-B06188-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338Q-B06188-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338Q-B06188-GM?

For technical support, including SI5338Q-B06188-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338Q-B06188-GM requirements.

6.How does Aetrix verify that SI5338Q-B06188-GM is sourced from the original manufacturer or authorized distributors?

All SI5338Q-B06188-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338Q-B06188-GM meets industry standards.

7.What is the process for return or replacement of SI5338Q-B06188-GM?

All SI5338Q-B06188-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5338Q-B06188-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338Q-B06188-GM part is unused and in its original packaging.

Return procedure for SI5338Q-B06188-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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