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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338Q-B06188-GMR

Name: SI5338Q-B06188-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338Q-B06188-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338Q-B06188-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338Q-B06188-GMR.pdf

Description:: I2C CONTROL, 4-OUTPUT, ANY FREQU

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338Q-B06188-GMR from Skyworks Solutions is an I²C-programmable quad clock generator IC with four independently configurable differential or single-ended outputs, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and operation across –40 to +85 °C. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA clock trees.

For engineers reviewing the SI5338Q-B06188-GMR datasheet, SI5338Q-B06188-GMR pinout, SI5338Q-B06188-GMR application, or SI5338Q-B06188-GMR equivalent, key selection considerations include its MultiSynth™-based any-frequency synthesis (0.16–710 MHz per output), independent output voltage support (1.5/1.8/2.5/3.3 V), flexible reference inputs (crystal, CMOS, SSTL, differential), and I²C/SMBus programmability with ClockBuilder Pro software integration.

Technical Context

The SI5338Q-B06188-GMR implements a two-stage PLL architecture: a high-stability integer-N PLL (Stage 1) locks to one of six input references, followed by four independent MultiSynth™ fractional-N synthesizers (Stage 2) generating each output. Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with per-output supply voltage control and programmable phase offset (<20 ps step resolution).

It features loss-of-lock and loss-of-signal monitoring, glitchless frequency increment/decrement (1 ppm steps), spread-spectrum clocking (0.5–5.0% spread, 33–63 kHz modulation), and external feedback mode for zero-delay operation. The device operates from a single 1.8/2.5/3.3 V core supply and delivers 45 mA typical core current at 100 MHz on all outputs with 25 MHz reference.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps - meets PCIe Gen 3 SRNS and Gen 4 common clock jitter requirements for high-reliability serial links
Output Frequency Range	0.16–710 MHz - covers Ethernet (125/156.25 MHz), PCIe (100 MHz), Fibre Channel (1.0625 GHz via Fvco/4), and broadcast video (27/74.25 MHz)
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - enables flexible system-level clock sourcing
Output Formats	LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL - allows direct interfacing to CPUs, FPGAs, switches, and SerDes without level-shifting buffers
Supply Voltages	VDD = 1.8/2.5/3.3 V; VDDOx = 1.5/1.8/2.5/3.3 V - supports mixed-voltage SoC/FPGA platforms with independent output rail control
Operating Temperature	–40 to +85 °C - qualified for industrial and telecom line card environments without derating
Package	24-pin QFN, 4 × 4 mm - space-constrained PCBs with thermal resistance θJA = 37 °C/W (still air)

Pinout & Package

The SI5338Q-B06188-GMR is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per the Si5338 family and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2, IN5, IN6	Differential clock inputs	Accept AC-coupled LVDS/LVPECL/CML references up to 710 MHz; require external 100 Ω termination
IN3, IN4	Single-ended clock inputs	Support CMOS/SSTL/HSTL references (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A/CLK0B to CLK3A/CLK3B	Differential output pairs	Four independent output drivers; each configurable for format, frequency, voltage, and phase
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V rails per output group - enables mixed-signal interface compatibility
VDD	Core supply	Single 1.8/2.5/3.3 V supply powering PLL, logic, and memory; PSRR optimized for noise immunity
SCL, SDA	I²C/SMBus interface	Standard 100/400 kHz operation; supports ClockBuilder Pro programming and runtime reconfiguration
INTR	Interrupt output	Open-drain status flag indicating loss-of-lock, loss-of-signal, or configuration error
RSVD_GND	Reserved ground	Internal test pin; must be connected to GND per layout guidelines to ensure signal integrity

Key Features

Feature	Design Value
MultiSynth™ synthesis	Enables true zero-ppm frequency accuracy on all four outputs simultaneously, eliminating crystal inventory and board space for multiple oscillators
Independent output voltage per driver	Permits direct connection to heterogeneous devices (e.g., 1.8 V FPGA I/O, 3.3 V switch PHY) without external level shifters
Glitchless frequency adjustment	1 ppm step size with hardware pin control (FINC/FDEC) or I²C allows real-time dynamic frequency scaling without clock interruption
Programmable phase offset	±45 ns range with <20 ps step resolution enables precise skew alignment across multi-lane interfaces (PCIe, DDR, SATA)
Spread spectrum clocking	Configurable 0.5–5.0% down-spread at 33–63 kHz reduces EMI peak emissions in dense PCB layouts without affecting timing margins

Applications

PCIe Gen 3/4 Root Complex	Ethernet Switch Timing
Use Scenario: Providing synchronized 100 MHz reference clocks to CPU, PCH, and add-in cards in server motherboards with strict PCIe Gen 4 jitter limits. IC Role / Device Role / Timing Role: Quad-output common clock generator meeting PCIe Gen 4 SRNS specification (≤0.45 ps RMS jitter) with independent output enable/disable. Use Value: Eliminates need for four discrete oscillators while maintaining sub-0.5 ps jitter across all lanes, reducing BOM cost and layout complexity.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE switch ASICs and PHYs in data center top-of-rack switches. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer supporting IEEE 802.3bj/ck jitter profiles via programmable MultiSynth™ outputs and low-noise PLL architecture. Use Value: Single-device solution for multi-rate Ethernet timing with deterministic phase relationships between ports, enabling precise packet timestamping.
FPGA-Based Video Processing	Telecom Line Card Synchronization
Use Scenario: Delivering pixel clocks (27 MHz, 74.25 MHz), reference clocks (148.5 MHz), and auxiliary timing (100 MHz) to Xilinx Versal or Intel Agilex FPGAs in broadcast video encoders. IC Role / Device Role / Timing Role: Configurable quad clock generator with CMOS and LVDS outputs, supporting SMPTE ST 2082-1 and ST 2110-10 timing requirements. Use Value: Replaces three separate oscillators and a fanout buffer; programmable phase offsets align video pipeline stages within ±20 ps.	Use Scenario: Distributing stratum-3 compliant 19.44 MHz, 155.52 MHz, and 622.08 MHz clocks across OTN framer, mapper, and PHY ICs in optical line cards. IC Role / Device Role / Timing Role: High-stability clock generator with OC-12-compliant jitter (≤1 ps RMS) and loss-of-signal alarm for network synchronization monitoring. Use Value: Meets Telcordia GR-1244-CORE jitter specs while enabling hot-swap clock source redundancy via dual reference inputs (IN1/IN2).

PCIe Gen 3/4 Root Complex

Ethernet Switch Timing

Use Scenario: Providing synchronized 100 MHz reference clocks to CPU, PCH, and add-in cards in server motherboards with strict PCIe Gen 4 jitter limits.

IC Role / Device Role / Timing Role: Quad-output common clock generator meeting PCIe Gen 4 SRNS specification (≤0.45 ps RMS jitter) with independent output enable/disable.

Use Value: Eliminates need for four discrete oscillators while maintaining sub-0.5 ps jitter across all lanes, reducing BOM cost and layout complexity.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE switch ASICs and PHYs in data center top-of-rack switches.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer supporting IEEE 802.3bj/ck jitter profiles via programmable MultiSynth™ outputs and low-noise PLL architecture.

Use Value: Single-device solution for multi-rate Ethernet timing with deterministic phase relationships between ports, enabling precise packet timestamping.

FPGA-Based Video Processing

Telecom Line Card Synchronization

Use Scenario: Delivering pixel clocks (27 MHz, 74.25 MHz), reference clocks (148.5 MHz), and auxiliary timing (100 MHz) to Xilinx Versal or Intel Agilex FPGAs in broadcast video encoders.

IC Role / Device Role / Timing Role: Configurable quad clock generator with CMOS and LVDS outputs, supporting SMPTE ST 2082-1 and ST 2110-10 timing requirements.

Use Value: Replaces three separate oscillators and a fanout buffer; programmable phase offsets align video pipeline stages within ±20 ps.

Use Scenario: Distributing stratum-3 compliant 19.44 MHz, 155.52 MHz, and 622.08 MHz clocks across OTN framer, mapper, and PHY ICs in optical line cards.

IC Role / Device Role / Timing Role: High-stability clock generator with OC-12-compliant jitter (≤1 ps RMS) and loss-of-signal alarm for network synchronization monitoring.

Use Value: Meets Telcordia GR-1244-CORE jitter specs while enabling hot-swap clock source redundancy via dual reference inputs (IN1/IN2).

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06188-GM	Higher integration: integrated crystal oscillator, lower jitter (0.35 ps RMS), 8 outputs, supports JESD204B deterministic latency	Targeted at JESD204B ADC/DAC timing and ultra-low-jitter 5G infrastructure; requires different layout and ClockBuilder Pro configuration	Select when sub-0.4 ps jitter, integrated XO, or >4 outputs are required; not pin-compatible
ICS853S01AGI-01LFT	Fixed-frequency 4-output LVDS buffer (no synthesis), 0.5 ps RMS jitter, 3.3 V only, no I²C interface	Limited to static clock distribution; no frequency translation, phase adjustment, or spread spectrum	Select only for simple fanout of existing clocks where programmability and flexibility are unnecessary

Compared with Si5332A-D06188-GM and ICS853S01AGI-01LFT, the SI5338Q-B06188-GMR uniquely balances programmability, jitter performance, and pin count in a compact QFN-making it optimal for PCIe/FPGA systems requiring field-upgradable timing without redesign.

Availability

SI5338Q-B06188-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 root complexes, Ethernet switch timing, and FPGA-based video processing requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production lots.

Supply support for SI5338Q-B06188-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The SI5338 product line was designed for high-performance, software-configurable clock generation in datacenter, telecom, and broadcast systems-emphasizing low jitter, multi-format outputs, and seamless integration with ClockBuilder Pro.

FAQ

What is the maximum output frequency supported by the SI5338Q-B06188-GMR?

The SI5338Q-B06188-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Frequencies above 350 MHz are limited to two unique values simultaneously (Fvco/4 and Fvco/6), as specified in the Si5338 datasheet Section 3.3. This capability enables direct clocking of high-speed SerDes blocks without external frequency multipliers.

Does the SI5338Q-B06188-GMR support PCIe Gen 4 timing requirements?

Yes, the SI5338Q-B06188-GMR meets PCIe Gen 4 common clock jitter specifications (≤0.45 ps RMS, 10 kHz–50 MHz) when configured per AN562 guidelines using HCSL outputs and appropriate reference input. Its MultiSynth™ architecture and low-phase-noise VCO deliver the stability required for 16 GT/s link training and reliable data recovery in endpoint and root complex applications.

How is the SI5338Q-B06188-GMR programmed and configured?

The SI5338Q-B06188-GMR is programmed via its I²C/SMBus interface using Skyworks' ClockBuilder Pro software, which auto-generates register maps, validates configurations, and exports .c files for embedded initialization. Configuration can also be performed in-system via microcontroller firmware or through dedicated pins (FINC/FDEC, OEB) for hardware-triggered frequency/phase adjustments without host intervention.

Can the SI5338Q-B06188-GMR operate with a single-ended input reference?

Yes, the SI5338Q-B06188-GMR accepts single-ended CMOS, SSTL, or HSTL references on pins IN3 and IN4 across 5–350 MHz. Input thresholds are referenced to VDD (VIH = 0.7×VDD, VIL = 0.3×VDD), and slew rate should exceed 1 V/ns for optimal jitter performance. No external biasing is required-internal termination and level detection are integrated.

What thermal management considerations apply to the SI5338Q-B06188-GMR?

The SI5338Q-B06188-GMR has a junction-to-ambient thermal resistance (θJA) of 37 °C/W in still air and requires a properly sized PCB copper pour connected to the exposed thermal pad. For continuous operation at full load (45 mA core current), ambient temperature must remain ≤+85 °C with ≥1 cm² of 2-oz copper under the package. Thermal vias (≥6×0.3 mm) to inner ground planes are recommended per Skyworks Application Note AN361.

SI5338Q-B06188-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338Q-B06188-GMR FAQ

1.How can I place an order for SI5338Q-B06188-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338Q-B06188-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338Q-B06188-GMR reliable?

The price and inventory of SI5338Q-B06188-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338Q-B06188-GMR is usually 5 days.

3.What payment methods are accepted for SI5338Q-B06188-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338Q-B06188-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338Q-B06188-GMR?

SI5338Q-B06188-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338Q-B06188-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338Q-B06188-GMR?

For technical support, including SI5338Q-B06188-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338Q-B06188-GMR requirements.

6.How does Aetrix verify that SI5338Q-B06188-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338Q-B06188-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338Q-B06188-GMR meets industry standards.

7.What is the process for return or replacement of SI5338Q-B06188-GMR?

All SI5338Q-B06188-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338Q-B06188-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338Q-B06188-GMR part is unused and in its original packaging.

Return procedure for SI5338Q-B06188-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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