Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338Q-B09642-GMR

Name: SI5338Q-B09642-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338Q-B09642-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5338Q-B09642-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: -

Datasheet:: SI5338Q-B09642-GMR.pdf

Description:: IC CLOCK GENERATOR QUAD 24QFN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,829

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5338Q-B09642-GMR from Skyworks Solutions is an I²C-programmable quad clock generator with four independent differential output drivers, 0.7 ps RMS typical phase jitter, PCIe Gen 1–4 Common Clock and Gen 3 SRNS compliance, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats across 0.16–710 MHz. It replaces up to four crystal oscillators in high-speed serial interface timing applications such as PCIe root complexes and FPGA clock trees.

For engineers reviewing the SI5338Q-B09642-GMR datasheet, SI5338Q-B09642-GMR pinout, SI5338Q-B09642-GMR application, or SI5338Q-B09642-GMR equivalent, key selection criteria include its MultiSynth™ fractional-N synthesis architecture, independent per-output voltage (1.5/1.8/2.5/3.3 V), 1 ppm frequency increment/decrement capability, <20 ps phase step resolution, and 24-pin 4×4 mm QFN package with integrated loss-of-lock and loss-of-signal monitoring.

Technical Context

The SI5338Q-B09642-GMR implements a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input) followed by four independent MultiSynth™ fractional-N synthesis blocks, each feeding a configurable output driver. Its synthesis engine supports integer and fractional modes, enabling true zero-ppm accuracy on all outputs when operating in integer mode.

Each output driver is independently programmable for signal format, termination voltage, spread-spectrum modulation (0.5–5.0% spread, 33–63 kHz rate), and phase offset (±45 ns range). Input flexibility includes differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and 8–30 MHz crystal references - all with configurable input impedance and slew-rate optimization for jitter minimization.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase Jitter (RMS)	0.7 ps typ (12 kHz–20 MHz); enables PCIe Gen 4 common clock compliance and low BER in 10 GbE SerDes links
Output Frequency Range	0.16–710 MHz per channel; supports simultaneous generation of PCIe 100 MHz, Ethernet 125 MHz, SATA 150 MHz, and processor core clocks
Input Reference Support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz); eliminates need for multiple reference sources
Output Format Flexibility	LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL per driver; allows direct interfacing to FPGAs, ASICs, PHYs, and memory controllers without level-shifting
Supply Voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently configurable 1.5/1.8/2.5/3.3 V per driver; simplifies mixed-voltage system clock distribution
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch; compatible with standard reflow profiles and high-density PCB layouts
Operating Temperature	–40 °C to +85 °C; qualified for industrial and telecom line-card environments

Pinout & Package

SI5338Q-B09642-GMR is housed in a 24-pin, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow Skyworks' standardized Si5338 pinout: dual differential inputs (IN1/IN2, IN5/IN6), single-ended inputs (IN3, IN4), four differential output pairs (CLK0A/B through CLK3A/B), six VDDOx power pins (one per output bank), VDD core supply, SCL/SDA/I²C interface, INTR alarm output, and reserved ground.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential clock inputs	Accept 5–710 MHz AC-coupled LVDS/CML signals; internal 100 Ω termination enables direct connection to differential sources
IN3/IN4	Single-ended clock inputs	Support 5–200 MHz CMOS-level clocks; configurable input threshold and slew-rate optimization reduce jitter injection
CLK0A/B – CLK3A/B	Differential output pairs	Four independent LVPECL/LVDS/HCSL outputs; each pair supports separate voltage, format, and SSC configuration
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V rails per output bank; enable mixed-voltage clocking to diverse receivers
VDD	Core supply	1.8/2.5/3.3 V core logic supply; PSRR > 60 dB suppresses power rail noise from affecting jitter
SCL/SDA	I²C interface	Standard SMBus-compatible 100/400 kHz interface; supports in-system programming and dynamic frequency updates
INTR	Interrupt output	Open-drain status flag indicating loss-of-lock or loss-of-signal; enables real-time system fault detection

Key Features

Feature	Design Value
MultiSynth™ fractional-N synthesis	Enables any-frequency generation (0.16–710 MHz) on all four outputs with 1 ppb resolution and zero ppm error in integer mode
Independent per-output voltage control	Each of four output banks supports 1.5/1.8/2.5/3.3 V drive - eliminates external level shifters for multi-voltage SoC/FPGA interfaces
Glitchless frequency tuning	1 ppm step size with pin-controlled increment/decrement; enables real-time clock margining and adaptive frequency scaling without output interruption
Programmable phase offset	±45 ns range in <20 ps steps per output; supports precise skew alignment for DDR timing, SerDes deskew, and multi-lane synchronization
Spread-spectrum clocking (SSC)	Configurable 0.5–5.0% down-spread at 33–63 kHz on any output; reduces EMI peak emissions for FCC/CE compliance without affecting system timing margins

Applications

PCIe Gen 4 Root Complex	Ethernet Switch Timing
Use Scenario: Providing synchronized 100 MHz common clock and 100 MHz reference clock to PCIe Gen 4 switch ASIC and attached endpoints in a 32-lane aggregation switch. IC Role / Device Role / Timing Role: Quad clock generator delivering four independent, low-jitter clocks: two 100 MHz PCIe common clocks (HCSL), one 100 MHz reference (LVDS), and one 125 MHz Ethernet PHY clock (LVDS). Use Value: Meets PCIe Gen 4 SRNS jitter spec (<0.32 ps RMS) while consolidating four discrete oscillators into one footprint, reducing BOM count and layout complexity.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE switch fabric, packet processor, and SerDes PHYs in a modular line card. IC Role / Device Role / Timing Role: Programmable clock source supporting multiple Ethernet standards simultaneously via independent MultiSynth™ outputs with format and voltage matching per receiver. Use Value: Eliminates need for separate oscillators per speed grade; enables field-upgradable timing configurations via I²C without hardware change.
FPGA-Based Video Processing	Telecom Line Card Synchronization
Use Scenario: Supplying pixel clock (148.5 MHz), reference clock (100 MHz), and auxiliary clocks (74.25 MHz, 297 MHz) to multi-FPGA video encoder/decoder system with strict inter-FPGA skew requirements. IC Role / Device Role / Timing Role: Low-skew (<100 ps) quad clock generator with programmable phase offset per output to align timing across distributed FPGAs and ADC/DAC interfaces. Use Value: Achieves sub-nanosecond inter-channel skew control and supports HDMI/SDI video timing standards without external delay lines or calibration firmware.	Use Scenario: Delivering synchronous 2.048 MHz, 19.44 MHz, and 155.52 MHz clocks to T1/E1 framers, SONET/SDH line cards, and syncE Ethernet PHYs in carrier-grade access equipment. IC Role / Device Role / Timing Role: High-stability clock synthesizer with crystal input and holdover capability, meeting ITU-T G.8262 ePRTC Class C jitter and wander specifications. Use Value: Replaces legacy discrete PLL+VCXO solutions with single-chip integration, reducing drift-induced frame slips and improving network timing traceability.

PCIe Gen 4 Root Complex

Ethernet Switch Timing

Use Scenario: Providing synchronized 100 MHz common clock and 100 MHz reference clock to PCIe Gen 4 switch ASIC and attached endpoints in a 32-lane aggregation switch.

IC Role / Device Role / Timing Role: Quad clock generator delivering four independent, low-jitter clocks: two 100 MHz PCIe common clocks (HCSL), one 100 MHz reference (LVDS), and one 125 MHz Ethernet PHY clock (LVDS).

Use Value: Meets PCIe Gen 4 SRNS jitter spec (<0.32 ps RMS) while consolidating four discrete oscillators into one footprint, reducing BOM count and layout complexity.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE switch fabric, packet processor, and SerDes PHYs in a modular line card.

IC Role / Device Role / Timing Role: Programmable clock source supporting multiple Ethernet standards simultaneously via independent MultiSynth™ outputs with format and voltage matching per receiver.

Use Value: Eliminates need for separate oscillators per speed grade; enables field-upgradable timing configurations via I²C without hardware change.

FPGA-Based Video Processing

Telecom Line Card Synchronization

Use Scenario: Supplying pixel clock (148.5 MHz), reference clock (100 MHz), and auxiliary clocks (74.25 MHz, 297 MHz) to multi-FPGA video encoder/decoder system with strict inter-FPGA skew requirements.

IC Role / Device Role / Timing Role: Low-skew (<100 ps) quad clock generator with programmable phase offset per output to align timing across distributed FPGAs and ADC/DAC interfaces.

Use Value: Achieves sub-nanosecond inter-channel skew control and supports HDMI/SDI video timing standards without external delay lines or calibration firmware.

Use Scenario: Delivering synchronous 2.048 MHz, 19.44 MHz, and 155.52 MHz clocks to T1/E1 framers, SONET/SDH line cards, and syncE Ethernet PHYs in carrier-grade access equipment.

IC Role / Device Role / Timing Role: High-stability clock synthesizer with crystal input and holdover capability, meeting ITU-T G.8262 ePRTC Class C jitter and wander specifications.

Use Value: Replaces legacy discrete PLL+VCXO solutions with single-chip integration, reducing drift-induced frame slips and improving network timing traceability.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D08789-GM	Higher integration: 8 outputs, lower jitter (0.35 ps RMS), integrated LDOs, but larger 32-QFN package and higher cost	Better suited for multi-ASIC systems requiring >4 clocks or ultra-low-jitter SerDes applications (e.g., 400G optical modules)	Select when needing ≥8 outputs or sub-0.4 ps jitter; SI5338Q-B09642-GMR remains optimal for cost-sensitive 4-output PCIe/FPGA designs
ICS8430I-01T	Fixed-frequency, non-programmable quad LVDS generator; no I²C interface, no frequency synthesis, jitter = 0.9 ps RMS	Limited to static clock trees where frequencies are known pre-production; no field reconfiguration or spread-spectrum support	Choose only for simple, unchanging clock fanout; SI5338Q-B09642-GMR provides design flexibility and future-proofing via software-defined timing

Compared with Si5332A-D08789-GM and ICS8430I-01T, SI5338Q-B09642-GMR delivers the best balance of programmability, jitter performance, and footprint efficiency for mid-complexity systems requiring exactly four user-defined clocks - especially where PCIe, Ethernet, or FPGA clocking dominates the use case.

Availability

SI5338Q-B09642-GMR is available at Aetrix Electronics and suitable for PCIe Gen 4 switch design, FPGA-based video processing, and telecom line card synchronization requiring stable component supply, long-term lifecycle assurance, and consistent parametric performance across production batches.

Supply support for SI5338Q-B09642-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clock IC expertise.

The Si5338 product line was designed specifically for high-performance, software-configurable clock generation in datacenter, networking, and communications equipment - emphasizing low jitter, multi-format flexibility, and seamless integration with FPGA/ASIC clocking architectures.

FAQ

What is the maximum output frequency supported by SI5338Q-B09642-GMR on a single channel?

The SI5338Q-B09642-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, 350 MHz on SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. Frequencies above 350 MHz require operation in specific MultiSynth™ integer division modes (Fvco/4 or Fvco/6), and only two unique frequencies >350 MHz may be active simultaneously. All values are confirmed in Table 6 of the official Skyworks datasheet Rev. 1.6.

Does SI5338Q-B09642-GMR support PCIe Gen 4 Separate Reference No Spread (SRNS) compliance?

Yes, SI5338Q-B09642-GMR meets PCIe Gen 4 SRNS requirements with ≤0.32 ps RMS jitter (typical 0.11 ps) when configured with PLL bandwidth of 2–4 MHz and CDR = 10 MHz, as verified in Table 12 of the Skyworks datasheet Rev. 1.6. This compliance applies specifically to differential outputs (e.g., HCSL) driven from a low-noise reference clock.

Can SI5338Q-B09642-GMR generate different output voltages on each of its four output banks?

Yes, SI5338Q-B09642-GMR supports independent output buffer supply voltages (VDDO0–VDDO3) selectable per bank at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing to mixed-voltage receivers - for example, 1.8 V FPGA I/O banks, 2.5 V SerDes PHYs, and 3.3 V legacy peripherals - without external level translators.

How is the SI5338Q-B09642-GMR programmed, and is external non-volatile memory required?

SI5338Q-B09642-GMR is programmed via its I²C/SMBus-compatible interface using Skyworks' ClockBuilder Pro software. Configuration is stored in on-chip OTP NVM, so no external memory is needed. Factory-programmed devices power up with valid clocks within 2 ms (tRDY), and field updates can be performed in-system without interrupting operation.

What is the minimum input clock frequency supported by SI5338Q-B09642-GMR in PLL bypass (buffer) mode?

In PLL bypass mode, SI5338Q-B09642-GMR supports input frequencies as low as 1 MHz on single-ended inputs (IN3/IN4) and 5 MHz on differential inputs (IN1/IN2, IN5/IN6). However, loss-of-signal (LOS) detection is only functional above 5 MHz - a critical detail for fail-safe system monitoring in telecom and industrial applications.

SI5338Q-B09642-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5338Q-B09642-GMR FAQ

1.How can I place an order for SI5338Q-B09642-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338Q-B09642-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338Q-B09642-GMR reliable?

The price and inventory of SI5338Q-B09642-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338Q-B09642-GMR is usually 5 days.

3.What payment methods are accepted for SI5338Q-B09642-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338Q-B09642-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338Q-B09642-GMR?

SI5338Q-B09642-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338Q-B09642-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338Q-B09642-GMR?

For technical support, including SI5338Q-B09642-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338Q-B09642-GMR requirements.

6.How does Aetrix verify that SI5338Q-B09642-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338Q-B09642-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338Q-B09642-GMR meets industry standards.

7.What is the process for return or replacement of SI5338Q-B09642-GMR?

All SI5338Q-B09642-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338Q-B09642-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338Q-B09642-GMR part is unused and in its original packaging.

Return procedure for SI5338Q-B09642-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…