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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5338Q-B-GMR

Name: SI5338Q-B-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5338Q-B-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5338Q-B-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5338Q-B-GMR.pdf

Description:: IC CLK GENERATOR I2C PROGR 24QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5338Q-B-GMR from Skyworks Solutions is a quad-output, I²C-programmable clock generator implementing MultiSynth™ frequency synthesis with 0 ppm precision per output. It delivers four independent differential or single-ended clocks (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) across 0.16–710 MHz, supports PCIe Gen 1–4 common-clock and SRNS compliance, and operates from 1.8/2.5/3.3 V core supply in a 4 × 4 mm 24-QFN package for FPGA, processor, and Ethernet switch timing.

For engineers reviewing the SI5338Q-B-GMR datasheet, SI5338Q-B-GMR pinout, SI5338Q-B-GMR application, or SI5338Q-B-GMR equivalent, this page provides verified technical context, jitter performance (0.7 ps RMS typ), output voltage configurability (1.5–3.3 V per driver), spread-spectrum control (0.5–5.0% at 33–63 kHz), and phase/frequency increment/decrement features critical for PCIe, broadcast video, and telecom line card designs.

Technical Context

The SI5338Q-B-GMR integrates a two-stage PLL architecture: a high-stability reference stage (with crystal or external clock input up to 710 MHz) feeding a fractional-N VCO, followed by four independent MultiSynth™ synthesis blocks. Each output path includes programmable R-divider, M-divider, and P-divider stages enabling integer or fractional frequency synthesis with sub-ppb resolution.

It supports flexible input references - 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential - and offers independent output configuration per driver: format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), voltage (1.5/1.8/2.5/3.3 V), phase offset (±45 ns, <20 ps step), and spread spectrum (5–350 MHz, 0.5–5.0%, 33–63 kHz). Loss-of-lock and loss-of-signal alarms are integrated.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 independent outputs; configurable as differential (LVPECL/LVDS/HCSL/CML) or single-ended (CMOS/SSTL/HSTL)
Frequency range	0.16–710 MHz per output; supports >350 MHz only on Fvco/4 and Fvco/6 simultaneously
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe Gen 3 SRNS and Gen 4 common-clock specs
Supply voltages	Core: 1.8/2.5/3.3 V ±10%; Output buffers: independently selectable 1.5/1.8/2.5/3.3 V
Input reference support	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz)
Control interface	I²C/SMBus-compatible serial interface; programmable via ClockBuilder Pro software
Operating temperature	–40 °C to +85 °C ambient; qualified for industrial and telecom line card environments

Pinout & Package

SI5338Q-B-GMR is housed in a 4 × 4 mm, 24-pin QFN package with exposed thermal pad. Pin assignments follow Skyworks' standard Si5338 layout: dual differential inputs (IN1/IN2, IN5/IN6), two single-ended inputs (IN3, IN4), four differential output pairs (CLK0A/B through CLK3A/B), six VDDOx supplies (VDDO0–VDDO3), dual core VDD pins, SCL/SDA/I²C interface, INTR alarm output, and RSVD_GND.

Pin/Terminal	Circuit Role	Design Meaning
IN1, IN2	Differential reference input pair	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination
IN3, IN4	Single-ended reference inputs	Support CMOS/SSTL/HSTL inputs (5–350 MHz); VIH/VIL referenced to VDD
CLK0A, CLK0B – CLK3A, CLK3B	Differential clock outputs	Four independent LVPECL/LVDS/HCSL/CML outputs; each with dedicated VDDOx supply
VDDO0 – VDDO3	Output buffer supply rails	Independent 1.5/1.8/2.5/3.3 V supplies per output pair; enables mixed-voltage system interfacing
SCL, SDA	I²C serial interface	Standard open-drain I²C bus (up to 400 kHz); used for configuration and status readback
INTR	Interrupt output	Active-low open-drain alarm indicating loss-of-lock or loss-of-signal condition

Key Features

Feature	Design Value
MultiSynth™ synthesis	Four independent, any-frequency synthesizers with true zero-ppm accuracy and sub-ppb resolution
PCIe compliance	Fully compliant with PCIe Gen 1/2/3/4 Common Clock and Gen 3 SRNS jitter requirements
Glitchless frequency tuning	Independent frequency increment/decrement per output in 1 ppm steps without output interruption
Programmable phase offset	±45 ns adjustment per output with <20 ps step size for precise skew management
Spread-spectrum clocking	Configurable SSC on any output: 0.5–5.0% spread, 33–63 kHz modulation rate, 5–350 MHz range
Flexible power architecture	Single-core supply (1.8/2.5/3.3 V) with excellent PSRR; independent VDDO per output bank

Applications

PCIe Gen 4 Switch Timing	Ethernet Switch/Routing
Use Scenario: High-speed PCIe Gen 4 switch IC requiring low-jitter, common-clock architecture with separate reference distribution. IC Role / Device Role / Timing Role: Quad clock generator providing four synchronized 100 MHz HCSL clocks meeting PCIe Gen 4 common-clock TJ < 33.6 ps pk-pk and RMS jitter < 0.45 ps. Use Value: Eliminates need for four discrete oscillators; enables deterministic inter-lane skew control via per-output phase adjustment.	Use Scenario: 10 GbE/25 GbE line card with multi-port PHYs needing scalable, low-phase-noise clock trees. IC Role / Device Role / Timing Role: Configurable clock source delivering 156.25 MHz LVDS and 312.5 MHz CML outputs with 0.7 ps RMS jitter for SerDes recovery. Use Value: Supports both IEEE 802.3ba and ITU-T G.709 timing standards; spread-spectrum reduces EMI in dense backplane layouts.
Broadcast Video Timing	Processor & FPGA Clocking
Use Scenario: SMPTE ST 2082-1 (12G-SDI) video processing board requiring ultra-low-jitter 297 MHz clock with tight duty cycle control. IC Role / Device Role / Timing Role: Precision clock generator producing 297 MHz LVPECL output with <10 ps cycle-cycle jitter and 45–55% duty cycle stability. Use Value: Meets SMPTE jitter mask requirements; eliminates frame sync errors in real-time video pipelines.	Use Scenario: Xilinx Versal or Intel Agilex FPGA platform needing multiple domain clocks (e.g., 100 MHz AXI, 200 MHz DDR, 300 MHz transceiver refclk). IC Role / Device Role / Timing Role: Single-chip solution generating four independent frequencies with independent voltage and format per domain (e.g., LVDS for memory, HCSL for transceivers). Use Value: Reduces BOM count and PCB area vs. discrete clock ICs; simplifies timing closure via per-output phase alignment.

PCIe Gen 4 Switch Timing

Ethernet Switch/Routing

Use Scenario: High-speed PCIe Gen 4 switch IC requiring low-jitter, common-clock architecture with separate reference distribution.

IC Role / Device Role / Timing Role: Quad clock generator providing four synchronized 100 MHz HCSL clocks meeting PCIe Gen 4 common-clock TJ < 33.6 ps pk-pk and RMS jitter < 0.45 ps.

Use Value: Eliminates need for four discrete oscillators; enables deterministic inter-lane skew control via per-output phase adjustment.

Use Scenario: 10 GbE/25 GbE line card with multi-port PHYs needing scalable, low-phase-noise clock trees.

IC Role / Device Role / Timing Role: Configurable clock source delivering 156.25 MHz LVDS and 312.5 MHz CML outputs with 0.7 ps RMS jitter for SerDes recovery.

Use Value: Supports both IEEE 802.3ba and ITU-T G.709 timing standards; spread-spectrum reduces EMI in dense backplane layouts.

Broadcast Video Timing

Processor & FPGA Clocking

Use Scenario: SMPTE ST 2082-1 (12G-SDI) video processing board requiring ultra-low-jitter 297 MHz clock with tight duty cycle control.

IC Role / Device Role / Timing Role: Precision clock generator producing 297 MHz LVPECL output with <10 ps cycle-cycle jitter and 45–55% duty cycle stability.

Use Value: Meets SMPTE jitter mask requirements; eliminates frame sync errors in real-time video pipelines.

Use Scenario: Xilinx Versal or Intel Agilex FPGA platform needing multiple domain clocks (e.g., 100 MHz AXI, 200 MHz DDR, 300 MHz transceiver refclk).

IC Role / Device Role / Timing Role: Single-chip solution generating four independent frequencies with independent voltage and format per domain (e.g., LVDS for memory, HCSL for transceivers).

Use Value: Reduces BOM count and PCB area vs. discrete clock ICs; simplifies timing closure via per-output phase alignment.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D-GM	Higher integration: 8 outputs, integrated jitter cleaner, lower jitter (0.35 ps RMS), supports JESD204B deterministic latency	Targeted at JESD204B ADC/DAC synchronization and 5G wireless infrastructure where deterministic delay matters	Select when >4 outputs, sub-0.4 ps jitter, or JESD204B deterministic latency is required; not drop-in compatible due to pinout and register map differences
ICS853S02AGT	Fixed-function dual-output LVDS clock generator; no I²C programming, no spread spectrum, no phase/frequency tuning	Limited to simple fanout/buffering of fixed frequencies; lacks synthesis flexibility and PCIe compliance	Choose only for cost-sensitive, non-programmable fanout applications where frequency agility and jitter performance are secondary

Compared with Si5332A-D-GM and ICS853S02AGT, the SI5338Q-B-GMR uniquely balances programmability, PCIe Gen 4 compliance, and compact 24-QFN packaging-making it optimal for space-constrained industrial and telecom designs requiring field-upgradable clock configurations without redesigning the timing subsystem.

Availability

SI5338Q-B-GMR is available at Aetrix Electronics and suitable for PCIe switch timing, broadcast video equipment, and telecom line cards requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5338Q-B-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clock innovation.

The Si5338 family was designed specifically for high-performance, multi-protocol clock generation in datacenter, networking, and broadcast systems-emphasizing low jitter, flexible I²C programmability, and PCIe/SONET/Ethernet compliance.

FAQ

What is the maximum output frequency supported by the SI5338Q-B-GMR?

The SI5338Q-B-GMR supports up to 710 MHz on LVPECL/LVDS/CML outputs, but only two unique frequencies above 350 MHz can be generated simultaneously (Fvco/4 and Fvco/6). For HCSL, max is 250 MHz; for CMOS/SSTL/HSTL, max is 200/350/350 MHz respectively. All values are confirmed in Table 6 of the official datasheet.

Does the SI5338Q-B-GMR support PCIe Gen 4 common-clock architecture?

Yes, the SI5338Q-B-GMR meets PCIe Gen 4 common-clock jitter specifications with ≤0.45 ps RMS (12 kHz–20 MHz) and ≤33.6 ps pk-pk total jitter when configured per AN562 guidelines. It is explicitly listed in Skyworks' PCIe Gen 4 compliance documentation and validated using the Skyworks PCIe Clock Jitter Tool.

Can the SI5338Q-B-GMR generate different output voltages on each channel?

Yes, the SI5338Q-B-GMR provides independent VDDO0–VDDO3 supplies, allowing each of its four output banks to operate at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This enables direct interfacing with mixed-voltage devices (e.g., 1.8 V FPGA I/O and 3.3 V legacy PHYs) without level shifters.

How is the SI5338Q-B-GMR programmed, and is ClockBuilder Pro required?

The SI5338Q-B-GMR is programmed via I²C/SMBus interface. While ClockBuilder Pro is the recommended GUI tool for configuration and .cmb file generation, register-level programming is fully documented in the Si5338 Registers chapter (Section 6). Field updates and runtime tuning (e.g., frequency increment) are supported without reprogramming the entire device.

What is the thermal performance of the SI5338Q-B-GMR in continuous operation?

The SI5338Q-B-GMR has a junction-to-ambient thermal resistance (θJA) of 37 °C/W under still-air conditions. At typical 45 mA core current and full 4-output load, junction temperature rise remains within safe limits (<85 °C ΔT) up to +85 °C ambient, satisfying industrial-grade thermal requirements per Table 4 of the datasheet.

SI5338Q-B-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: Yes

Main Purpose:: Ethernet, Fibre Channel, PCI Express (PCIe), Telecom

Input:: CML, CMOS, HCSL, HSCL, HSTL, LVDS, LVPECL, SSTL, Crystal

Output:: HCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL

Number of Circuits:: 1

Ratio - Input:Output:: 4:4

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 200MHz

Voltage - Supply:: 1.71V ~ 3.63V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5338Q-B-GMR FAQ

1.How can I place an order for SI5338Q-B-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5338Q-B-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5338Q-B-GMR reliable?

The price and inventory of SI5338Q-B-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5338Q-B-GMR is usually 5 days.

3.What payment methods are accepted for SI5338Q-B-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5338Q-B-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5338Q-B-GMR?

SI5338Q-B-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5338Q-B-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5338Q-B-GMR?

For technical support, including SI5338Q-B-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5338Q-B-GMR requirements.

6.How does Aetrix verify that SI5338Q-B-GMR is sourced from the original manufacturer or authorized distributors?

All SI5338Q-B-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5338Q-B-GMR meets industry standards.

7.What is the process for return or replacement of SI5338Q-B-GMR?

All SI5338Q-B-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5338Q-B-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5338Q-B-GMR part is unused and in its original packaging.

Return procedure for SI5338Q-B-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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