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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5340D-D-GMR

Name: SI5340D-D-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5340D-D-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5340D-D-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5340D-D-GMR.pdf

Description:: IC BASE/BLANK PROTOTYPE 44QFN

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Product details

Overview

SI5340D-D-GMR from Skyworks Solutions is a 4-output, any-frequency clock generator with ultra-low 90 fs rms phase jitter, supporting differential (100 Hz–350 MHz) and LVCMOS (100 Hz–250 MHz) outputs, programmable signal formats (LVDS/LVPECL/CML/HCSL/LVCMOS), and zero-delay mode for FPGA, Ethernet switch, and OTN processor clocking.

For engineers reviewing the SI5340D-D-GMR datasheet, SI5340D-D-GMR pinout, SI5340D-D-GMR application, or SI5340D-D-GMR equivalent, this page delivers verified technical context, real-world design meaning of key specs, validated pin functions, confirmed alternative options, and supply support for industrial timing-critical designs.

Technical Context

The SI5340D-D-GMR integrates a wide-band PLL with MultiSynth™ fractional synthesis to generate up to four independent output frequencies from a single input-crystal (25–54 MHz), differential clock (10–750 MHz), or LVCMOS clock (10–250 MHz)-with integer/fractional division and glitchless on-the-fly frequency changes.

It supports zero-delay mode via external feedback to FB_IN, DCO operation with 0.001 ppb resolution, and fully configurable output drivers with independent VDDO pins (1.8/2.5/3.3 V), programmable common-mode voltage, and synchronous/asynchronous output disable control.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	4 independent differential or LVCMOS outputs
Max output frequency	350 MHz (differential); enables high-speed SerDes and memory interfaces
Phase jitter (rms)	90 fs (12 kHz–20 MHz); meets stringent jitter budgets for 10G/25G Ethernet and OTN
Input support	Crystal (25–54 MHz), differential (10–750 MHz), LVCMOS (10–250 MHz); eliminates need for external XO in many designs
Supply voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%; supports low-power system integration
Operating temp	–40 °C to +85 °C; qualified for industrial and telecom infrastructure environments
Package	44-QFN 7×7 mm; compact footprint with thermal pad for reliable power dissipation

Pinout & Package

SI5340D-D-GMR uses a 44-pin QFN package (7×7 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5340 Rev D datasheet Section 9 (Pin Descriptions).

Pin/Terminal	Circuit Role	Design Meaning
XA/XB	Crytal oscillator input	Accepts 25–54 MHz fundamental-mode crystal; internal load caps configurable
IN0/IN1/IN2	Differential/single-ended clock inputs	Supports 10–750 MHz differential or 10–250 MHz LVCMOS; selectable via IN_SEL[1:0] or register
FB_IN/FB_INb	External feedback input	Required for zero-delay mode; must be AC-coupled differential path
OUT0–OUT3	Differential clock outputs	Each independently configurable as LVDS/LVPECL/CML/HCSL/LVCMOS with programmable amplitude and VDDO
OEb	Output enable/disable control	Active-low global enable; supports synchronous/asynchronous disable to prevent runt pulses
RSTb	Hard reset input	Resets all registers to NVM defaults; initiates full initialization sequence
INTRb	Interrupt output	Open-drain status flag for LOS/LOL events; maskable per channel
I2C_SEL	Interface selection	High = I²C mode; low = SPI mode (3- or 4-wire); enables host voltage flexibility (1.8/3.3 V)

Key Features

Feature	Design Value
Any-frequency synthesis	Generates any output frequency (100 Hz–350 MHz) from any input (crystal or clock), eliminating discrete clock trees
Zero-delay mode	Enables fixed, minimal input-to-output delay by closing PLL loop externally-critical for deterministic latency in packet processing
Digital-controlled oscillator (DCO)	0.001 ppb frequency step resolution via FINC/FDEC pins or direct register writes-supports real-time margining and FIFO rate matching
Independent output supply pins	VDDO0–VDDO3 allow mixed-voltage clocking (e.g., 1.8 V for FPGA core, 3.3 V for PHY interface) without level shifters
In-circuit NVM programming	Two-time OTP memory stores power-up configuration; enables factory pre-programming or field updates without external programmer

Applications

High-Speed FPGA Clocking	Ethernet Switch Timing
Use Scenario: Providing multiple synchronized clocks to FPGA fabric, transceivers, and memory controllers in 10G/25G switch line cards. IC Role / Device Role / Timing Role: Single-chip clock tree replacing discrete XOs, buffers, and translators-generating 156.25 MHz (SerDes), 100 MHz (logic), and 300 MHz (DDR4) simultaneously. Use Value: Reduces BOM count by ≥7 components and eliminates inter-clock skew between domains via shared PLL reference.	Use Scenario: Synchronizing packet processing ASICs, MACs, and PHYs in enterprise and data center switches. IC Role / Device Role / Timing Role: Delivering low-jitter 125 MHz (IEEE 802.3), 250 MHz (PCS), and 100 MHz (management interface) with independent format control (LVDS for ASIC, LVCMOS for microcontroller). Use Value: Meets IEEE 802.3 jitter compliance (< 0.3 ps RMS) while enabling mixed-signal voltage domains on one board.
OTN Framer/Mapper Timing	Broadcast Video Sync
Use Scenario: Clocking OTN framers (e.g., TI TSB8104), mappers, and forward error correction engines in optical transport equipment. IC Role / Device Role / Timing Role: Generating precise 155.52 MHz (STM-1), 622.08 MHz (STM-4), and 1.244 Gbps line-rate clocks with sub-100 fs jitter to maintain BER < 10⁻¹². Use Value: Enables direct synthesis of ITU-T G.823/G.825 compliant clocks without external dividers or jitter cleaners.	Use Scenario: Distributing genlock, frame sync, and pixel clocks across SDI encoders, video processors, and HDMI transmitters in broadcast production gear. IC Role / Device Role / Timing Role: Producing 27 MHz (SMPTE ST 292), 74.25 MHz (HD-SDI), and 148.5 MHz (3G-SDI) with identical phase alignment across all outputs. Use Value: Eliminates frame tearing and lip-sync errors by guaranteeing < 50 ps inter-channel skew across all video timing domains.

High-Speed FPGA Clocking

Ethernet Switch Timing

Use Scenario: Providing multiple synchronized clocks to FPGA fabric, transceivers, and memory controllers in 10G/25G switch line cards.

IC Role / Device Role / Timing Role: Single-chip clock tree replacing discrete XOs, buffers, and translators-generating 156.25 MHz (SerDes), 100 MHz (logic), and 300 MHz (DDR4) simultaneously.

Use Value: Reduces BOM count by ≥7 components and eliminates inter-clock skew between domains via shared PLL reference.

Use Scenario: Synchronizing packet processing ASICs, MACs, and PHYs in enterprise and data center switches.

IC Role / Device Role / Timing Role: Delivering low-jitter 125 MHz (IEEE 802.3), 250 MHz (PCS), and 100 MHz (management interface) with independent format control (LVDS for ASIC, LVCMOS for microcontroller).

Use Value: Meets IEEE 802.3 jitter compliance (< 0.3 ps RMS) while enabling mixed-signal voltage domains on one board.

OTN Framer/Mapper Timing

Broadcast Video Sync

Use Scenario: Clocking OTN framers (e.g., TI TSB8104), mappers, and forward error correction engines in optical transport equipment.

IC Role / Device Role / Timing Role: Generating precise 155.52 MHz (STM-1), 622.08 MHz (STM-4), and 1.244 Gbps line-rate clocks with sub-100 fs jitter to maintain BER < 10⁻¹².

Use Value: Enables direct synthesis of ITU-T G.823/G.825 compliant clocks without external dividers or jitter cleaners.

Use Scenario: Distributing genlock, frame sync, and pixel clocks across SDI encoders, video processors, and HDMI transmitters in broadcast production gear.

IC Role / Device Role / Timing Role: Producing 27 MHz (SMPTE ST 292), 74.25 MHz (HD-SDI), and 148.5 MHz (3G-SDI) with identical phase alignment across all outputs.

Use Value: Eliminates frame tearing and lip-sync errors by guaranteeing < 50 ps inter-channel skew across all video timing domains.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5340C-D-GM1	Integer-only synthesis mode (no fractional MultiSynth); same 4-output, 350 MHz max, 44-QFN package	Lacks any-frequency flexibility; suitable only when all required outputs are integer multiples of input	Select when deterministic jitter floor is prioritized over frequency agility and configuration simplicity
LMK04832RHAR	2-input/14-output; dual-loop architecture; higher power; supports JESD204B subclass 1	Targets high-speed data converter timing; includes integrated LDOs and deterministic latency features not in SI5340D-D-GMR	Choose for RF/data converter systems requiring sub-nanosecond deterministic delay and multi-device synchronization

Compared with Si5340C-D-GM1, SI5340D-D-GMR adds fractional synthesis for arbitrary frequency generation without external dividers; versus LMK04832RHAR, it offers lower power and smaller footprint but lacks JESD204B-specific features and deterministic latency control.

Availability

SI5340D-D-GMR is available at Aetrix Electronics and suitable for FPGA clocking, Ethernet switching, and OTN framer applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for industrial and telecom deployments.

Supply support for SI5340D-D-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a U.S.-based semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog products.

The Si5340 family is designed as a highly configurable, low-jitter clock generator platform targeting high-speed digital systems-including networking, computing, and broadcast-where flexible, multi-format clock distribution replaces legacy discrete timing architectures.

FAQ

What is the maximum differential output frequency supported by the SI5340D-D-GMR?

The SI5340D-D-GMR supports a maximum differential output frequency of 350 MHz, as specified in Skyworks' Si5340 Rev D Ordering Guide for the "D" variant. This limit applies to all differential formats (LVDS, LVPECL, CML, HCSL) and is distinct from the 1028 MHz capability of higher-grade variants like Si5340A-D-GM1. The 350 MHz ceiling ensures optimal jitter performance and stability within the device's fractional synthesis architecture.

Does the SI5340D-D-GMR support zero-delay mode, and how is it implemented?

Yes, the SI5340D-D-GMR supports zero-delay mode. It is implemented by opening the internal PLL feedback loop and routing one output (recommended: OUT3) back to the FB_IN/FB_INb pins via an AC-coupled differential path. This external feedback cancels internal propagation delays, achieving fixed and minimal input-to-output latency-critical for deterministic timing in packet processors and FPGAs. Configuration requires specific register settings per Skyworks Application Note AN913.

Can the SI5340D-D-GMR generate both differential and LVCMOS outputs simultaneously?

Yes, the SI5340D-D-GMR can generate differential and LVCMOS outputs simultaneously. Each of its four outputs (OUT0–OUT3) is independently configurable as LVDS, LVPECL, CML, HCSL, or LVCMOS. LVCMOS outputs support 1.8 V, 2.5 V, or 3.3 V swing via dedicated VDDO pins, enabling mixed-signal clocking-for example, LVDS for an ASIC and LVCMOS for a microcontroller on the same board-without external level shifters.

What serial interfaces does the SI5340D-D-GMR support for configuration?

The SI5340D-D-GMR supports both I²C and SPI serial interfaces for configuration. Interface selection is controlled by the I2C_SEL pin: high enables I²C (standard/fast-mode), low enables SPI (3- or 4-wire). Both interfaces operate with 1.8 V or 3.3 V host logic levels, and register access allows full control of frequency planning, output formatting, fault monitoring, and DCO operation-enabling in-system programming and dynamic reconfiguration.

Is factory pre-programming available for the SI5340D-D-GMR, and how is it ordered?

Yes, factory pre-programming is available for the SI5340D-D-GMR using Skyworks' ClockBuilder Pro software. Users configure their timing solution online, generate a custom part number (e.g., SI5340D-Dxxxxx-GMR), and order directly through Skyworks or authorized distributors. The configuration is written to the device's one-time-programmable (OTP) NVM, enabling immediate clock generation at power-up without host intervention-ideal for volume production and systems lacking serial programming capability.

SI5340D-D-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5340D-D-GMR FAQ

1.How can I place an order for SI5340D-D-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5340D-D-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5340D-D-GMR reliable?

The price and inventory of SI5340D-D-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5340D-D-GMR is usually 5 days.

3.What payment methods are accepted for SI5340D-D-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5340D-D-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5340D-D-GMR?

SI5340D-D-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5340D-D-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5340D-D-GMR?

For technical support, including SI5340D-D-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5340D-D-GMR requirements.

6.How does Aetrix verify that SI5340D-D-GMR is sourced from the original manufacturer or authorized distributors?

All SI5340D-D-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5340D-D-GMR meets industry standards.

7.What is the process for return or replacement of SI5340D-D-GMR?

All SI5340D-D-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5340D-D-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5340D-D-GMR part is unused and in its original packaging.

Return procedure for SI5340D-D-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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