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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5341A-D10654-GM

Name: SI5341A-D10654-GM
Brand: Skyworks Solutions Inc.
SKU: SI5341A-D10654-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5341A-D10654-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5341A-D10654-GM.pdf

Description:: IC CLOCK GENERATOR PLL 64QFN

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Product details

Overview

SI5341A-D10654-GM from Skyworks Solutions is a 10-output, any-frequency clock generator with ultra-low 90 fs rms phase jitter, integer/fractional synthesis up to 1028 MHz, and independent LVDS/LVPECL/LVCMOS/CML/HCSL output formatting per channel. It replaces multiple XOs, buffers, and translators in FPGA, Ethernet switch, and OTN processor clock trees.

For engineers reviewing the SI5341A-D10654-GM datasheet, SI5341A-D10654-GM pinout, SI5341A-D10654-GM application, or SI5341A-D10654-GM equivalent, this page delivers verified technical context, real-world design meaning for key specs, validated pin functions, confirmed alternatives, and supply support for industrial and telecom timing designs.

Technical Context

The SI5341A-D10654-GM integrates a wide-band PLL with proprietary MultiSynth™ fractional synthesizers to generate precise, glitchless frequencies from 100 Hz to 1028 MHz on each of its 10 differential outputs. Its architecture supports zero-delay mode via external FB_IN feedback and DCO operation with 0.001 ppb frequency step resolution.

Input flexibility includes crystal (25–54 MHz), differential clock (10–750 MHz), or LVCMOS clock (10–250 MHz); outputs are independently configurable with programmable amplitude, common-mode voltage, and polarity across LVDS, LVPECL, CML, HCSL, and LVCMOS formats using dedicated VDDO pins.

Key Specifications

Parameter	Value and Actual Design Meaning
Phase jitter (rms)	90 fs - enables clean sampling in high-speed SerDes and ADCs without added timing margin
Output count	10 differential clocks - eliminates need for discrete fanout buffers in complex clock trees
Max output frequency	1028 MHz - supports PCIe Gen5, DDR5, and 100G/400G Ethernet PHY clocking
Synthesis mode	Integer and fractional - allows exact generation of non-integer-related frequencies like 156.25 MHz, 122.88 MHz, 245.76 MHz
Input options	Crystal (25–54 MHz), diff clock (10–750 MHz), LVCMOS (10–250 MHz) - accommodates XO, oscillator, or system clock reference
Output formats	LVDS, LVPECL, CML, HCSL, LVCMOS - matches diverse receiver requirements without level-shifting components
Supply voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, independent VDDO per output - enables mixed-voltage board design

Pinout & Package

SI5341A-D10654-GM is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions align with Si5341A-D-GM family specification and include dedicated input selection, status monitoring, serial interface, and 10 fully configurable differential output pairs.

Pin/Terminal	Circuit Role	Design Meaning
XA/XB	Crystal oscillator input	Accepts 25–54 MHz fundamental-mode crystal; internal load caps configurable for CL matching
IN0/IN0b, IN1/IN1b, IN2/IN2b	Differential input clocks	Supports 10–750 MHz differential signals; selectable as primary reference via IN_SEL[1:0] or register
FB_IN/FB_INb	External feedback input	Required for zero-delay mode; must be AC-coupled differential path with matched trace length
OUT0–OUT9 (each with x/xb)	Differential clock outputs	Each pair independently programmable for format, amplitude, VCM, and enable/disable behavior
OEb	Global output enable	Active-low hardware control; synchronous/asynchronous disable modes configurable per output
I2C_SCL/I2C_SDA or SPI_CS/SPI_SCLK/SPI_MOSI/SPI_MISO	Serial configuration interface	I2C or SPI selectable via I2C_SEL pin; supports in-circuit programming and NVM write (2× lifetime)
LOLb, INTRb	Status interrupt outputs	Open-drain flags for PLL lock loss and fault events; maskable via register

Key Features

Feature	Design Value
Any-frequency synthesis	Generates exact output frequencies (e.g., 122.88 MHz, 156.25 MHz, 245.76 MHz) from any input without external dividers
Glitchless on-the-fly reconfiguration	Changes output frequency mid-operation with zero cycle slips-critical for dynamic FPGA reconfiguration or CPU DVFS
Programmable output termination	Supports AC/DC-coupled LVDS, LVPECL, HCSL, and CML with user-defined VCM and swing-eliminates external bias networks
In-circuit NVM programming	Two-time OTP memory stores power-up configuration; enables factory pre-programming or field updates without special equipment
Zero-delay mode	Uses external FB_IN feedback to cancel internal path delay-ensures deterministic, minimal input-to-output latency for timing-critical loops

Applications

FPGA Clock Distribution	Ethernet Switch Timing
Use Scenario: Synchronizing multiple high-speed transceivers, memory controllers, and logic blocks within a Xilinx Versal or Intel Agilex FPGA. IC Role / Device Role / Timing Role: Central clock tree generator providing 10 precisely aligned, low-jitter clocks-including 156.25 MHz for 10G/25G Ethernet, 245.76 MHz for CPRI/eCPRI, and 122.88 MHz for JESD204B. Use Value: Replaces 4–6 discrete oscillators and buffers while maintaining sub-100 fs jitter integrity across all domains.	Use Scenario: Clocking line cards and switching fabric in 100G/400G data center switches requiring IEEE 1588 PTP synchronization and deterministic latency. IC Role / Device Role / Timing Role: Generates synchronized 100 MHz, 156.25 MHz, and 312.5 MHz clocks for MAC, PHY, and packet processing units with zero-delay mode enabled on critical paths. Use Value: Enables <1 ns input-to-output delay consistency across temperature and voltage-meeting ITU-T G.8262 EEC-2 compliance.
OTN Framer/Mapper Systems	Broadcast Video Processing
Use Scenario: Providing reference clocks for OTN framers (e.g., TI TSB4311), mappers, and forward error correction engines in optical transport terminals. IC Role / Device Role / Timing Role: Delivers 125 MHz, 155.52 MHz, 622.08 MHz, and 2488.32 MHz clocks with <±0.1 ppm accuracy and <90 fs jitter to meet G.709 frame alignment requirements. Use Value: Eliminates inter-clock skew between STS-1, OC-48, and OC-192 domains-reducing bit error rate in long-haul transmission.	Use Scenario: Driving SDI serializers, video processors, and HDMI transmitters in broadcast-grade cameras and production switchers requiring SMPTE 2081/2082 compliance. IC Role / Device Role / Timing Role: Supplies 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks with LVDS outputs matched to coaxial cable impedance and jitter below SMPTE ST 2059-2 Class A limit. Use Value: Prevents visible artifacts (jitter-induced color banding, frame sync loss) by delivering stable, low-phase-noise timing at 3G-SDI rates.

FPGA Clock Distribution

Ethernet Switch Timing

Use Scenario: Synchronizing multiple high-speed transceivers, memory controllers, and logic blocks within a Xilinx Versal or Intel Agilex FPGA.

IC Role / Device Role / Timing Role: Central clock tree generator providing 10 precisely aligned, low-jitter clocks-including 156.25 MHz for 10G/25G Ethernet, 245.76 MHz for CPRI/eCPRI, and 122.88 MHz for JESD204B.

Use Value: Replaces 4–6 discrete oscillators and buffers while maintaining sub-100 fs jitter integrity across all domains.

Use Scenario: Clocking line cards and switching fabric in 100G/400G data center switches requiring IEEE 1588 PTP synchronization and deterministic latency.

IC Role / Device Role / Timing Role: Generates synchronized 100 MHz, 156.25 MHz, and 312.5 MHz clocks for MAC, PHY, and packet processing units with zero-delay mode enabled on critical paths.

Use Value: Enables <1 ns input-to-output delay consistency across temperature and voltage-meeting ITU-T G.8262 EEC-2 compliance.

OTN Framer/Mapper Systems

Broadcast Video Processing

Use Scenario: Providing reference clocks for OTN framers (e.g., TI TSB4311), mappers, and forward error correction engines in optical transport terminals.

IC Role / Device Role / Timing Role: Delivers 125 MHz, 155.52 MHz, 622.08 MHz, and 2488.32 MHz clocks with <±0.1 ppm accuracy and <90 fs jitter to meet G.709 frame alignment requirements.

Use Value: Eliminates inter-clock skew between STS-1, OC-48, and OC-192 domains-reducing bit error rate in long-haul transmission.

Use Scenario: Driving SDI serializers, video processors, and HDMI transmitters in broadcast-grade cameras and production switchers requiring SMPTE 2081/2082 compliance.

IC Role / Device Role / Timing Role: Supplies 27 MHz, 74.25 MHz, and 148.5 MHz pixel clocks with LVDS outputs matched to coaxial cable impedance and jitter below SMPTE ST 2059-2 Class A limit.

Use Value: Prevents visible artifacts (jitter-induced color banding, frame sync loss) by delivering stable, low-phase-noise timing at 3G-SDI rates.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5341B-D-GM	Same 10-output architecture but limited to 350 MHz max output frequency and no fractional synthesis	Suitable only for sub-350 MHz applications (e.g., legacy Ethernet, SATA, USB); cannot generate 1028 MHz PCIe Gen5 clocks	Select when cost sensitivity outweighs frequency flexibility and jitter performance is secondary
LMK04832RHAR	2 dual-loop PLL architecture with 14 outputs; higher integrated phase noise floor (110 fs rms) and fixed 3.3 V core supply	Requires external loop filter components; better suited for RF-synthesizer hybrid use cases than pure clock tree replacement	Choose when needing cascaded jitter cleaning or multi-tier PLL distribution not supported by single-PLL Si5341

Compared with SI5341A-D10654-GM, Si5341B-D-GM sacrifices frequency range and synthesis flexibility for lower unit cost, while LMK04832RHAR adds architectural complexity and jitter overhead to support advanced RF timing-but neither offers the same combination of 1028 MHz capability, 90 fs jitter, and software-driven configurability in a single-chip solution.

Availability

SI5341A-D10654-GM is available at Aetrix Electronics and suitable for FPGA clock distribution, Ethernet switch timing, OTN framer systems, broadcast video processing, and test instrumentation requiring stable component supply and guaranteed long-term lifecycle support.

Supply support for SI5341A-D10654-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog ICs.

The Si5341 product line was designed specifically for high-performance, multi-output clock generation in datacenter, telecom infrastructure, and broadcast equipment-emphasizing ultra-low jitter, software-configurable flexibility, and single-chip clock tree consolidation.

FAQ

What is the maximum output frequency supported by the SI5341A-D10654-GM?

The SI5341A-D10654-GM supports differential output frequencies up to 1028 MHz. This capability enables direct clocking of PCIe Gen5 PHYs, DDR5 memory interfaces, and 400G Ethernet SerDes without external frequency multipliers. The device maintains sub-100 fs rms phase jitter even at these high frequencies due to its optimized MultiSynth™ fractional divider architecture and low-noise PLL design.

Does the SI5341A-D10654-GM support zero-delay mode, and how is it implemented?

Yes, the SI5341A-D10654-GM supports zero-delay mode via external feedback to the FB_IN/FB_INb pins. This mode requires AC-coupled differential connection from one output (recommended: OUT9) back to FB_IN to close the loop externally, canceling internal path delays. The implementation achieves deterministic, temperature-stable input-to-output latency-critical for time-sensitive applications like IEEE 1588 boundary clocks and OTN frame alignment circuits.

Can the SI5341A-D10654-GM generate both integer and non-integer related output frequencies simultaneously?

Yes, the SI5341A-D10654-GM uses independent MultiSynth™ fractional synthesizers per output, enabling simultaneous generation of arbitrary frequencies-including 122.88 MHz (for JESD204B), 156.25 MHz (for Ethernet), and 245.76 MHz (for CPRI)-from a single 25 MHz crystal input. Each output's numerator/denominator ratio is programmable, ensuring zero ppm error and no need for external dividers or VCXOs.

What serial interfaces does the SI5341A-D10654-GM support for configuration?

The SI5341A-D10654-GM supports both I2C and SPI serial interfaces for register configuration and status monitoring. Interface selection is controlled by the I2C_SEL pin. SPI operates in 3-wire or 4-wire mode and supports 1.8 V or 3.3 V host logic levels. Both interfaces allow full in-circuit programming, including two-time NVM writes for factory or field pre-programming of power-up configurations.

How many independent output voltage supplies does the SI5341A-D10654-GM require?

The SI5341A-D10654-GM requires one core supply (VDD = 1.8 V ±5%), one analog supply (VDDA = 3.3 V ±5%), and up to 10 independent VDDO pins-one per output driver. Each VDDO pin sets the output swing level (1.8 V, 2.5 V, or 3.3 V) and enables mixed-voltage clock distribution to different receivers on the same board without level shifters.

SI5341A-D10654-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

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SI5341A-D10654-GM FAQ

1.How can I place an order for SI5341A-D10654-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5341A-D10654-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5341A-D10654-GM reliable?

The price and inventory of SI5341A-D10654-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5341A-D10654-GM is usually 5 days.

3.What payment methods are accepted for SI5341A-D10654-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5341A-D10654-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5341A-D10654-GM?

SI5341A-D10654-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5341A-D10654-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5341A-D10654-GM?

For technical support, including SI5341A-D10654-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5341A-D10654-GM requirements.

6.How does Aetrix verify that SI5341A-D10654-GM is sourced from the original manufacturer or authorized distributors?

All SI5341A-D10654-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5341A-D10654-GM meets industry standards.

7.What is the process for return or replacement of SI5341A-D10654-GM?

All SI5341A-D10654-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5341A-D10654-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5341A-D10654-GM part is unused and in its original packaging.

Return procedure for SI5341A-D10654-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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