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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5341B-B03628-GM

Name: SI5341B-B03628-GM
Brand: Skyworks Solutions Inc.
SKU: SI5341B-B03628-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5341B-B03628-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 64-VFQFN Exposed Pad

Datasheet:: SI5341B-B03628-GM.pdf

Description:: IC PRE PROGRAMMED CLK GEN 64QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5341B-B03628-GM from Skyworks is a programmable ultra-low-jitter any-frequency clock generator with 10 independent outputs, integrated DSPLL and MultiSynth™ fractional synthesis, supporting 100 Hz–712.5 MHz output frequencies per channel, 0 ppm synthesis error, and in-circuit NVM programming for power-up configuration. It serves as a high-precision timing source in multi-clock-domain systems such as 5G baseband units and high-speed data converters.

For engineers reviewing the SI5341B-B03628-GM datasheet, SI5341B-B03628-GM pinout, SI5341B-B03628-GM application, or SI5341B-B03628-GM equivalent, this page delivers verified technical context, exact pin functions, real-world use cases, and validated alternative options - all grounded in Skyworks' Si5341 Rev D Family Reference Manual and official device specifications.

Technical Context

The SI5341B-B03628-GM implements a dual-stage architecture: a DSPLL locks to one of four inputs (XA/XB crystal or IN0–IN2 clocks), then feeds five independent MultiSynth™ fractional-N dividers (N0–N4) each driving up to two outputs via crosspoint routing and configurable R-dividers. Each output supports independent VDDO supply and signal format selection (LVPECL/LVDS/HCSL/CML/LVCMOS).

It features fully integrated loop filtering, zero-delay mode, dynamic frequency reconfiguration via I²C/SPI without PLL reset, and fault monitoring with LOL/LOSXAB/INTRb status signals. The device uses 44-bit numerator / 32-bit denominator fractional division for sub-Hz resolution and <100 fs RMS jitter (12 kHz–20 MHz) at 156.25 MHz.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	10 independent outputs with per-output format, VDDO, and enable control.
Frequency range	100 Hz to 712.5 MHz per output - enables precise generation of Ethernet, PCIe, SerDes, and ADC/DAC sampling clocks.
RMS jitter (12 kHz–20 MHz)	95 fs typical at 156.25 MHz - meets OC-192 SONET and 100G KR4 compliance requirements.
Input reference support	Crystal (25 MHz or 48–54 MHz on XA/XB) or external clock on XA/XB, IN0, IN1, IN2 - allows flexible system-level timing hierarchy.
Programmability	In-circuit programmable NVM with 2 user banks - enables field updates and power-up with custom configuration without external EEPROM.
Interface	I²C (up to 400 kHz) and SPI (up to 50 MHz) - supports both embedded host MCU and production-line programming.
Supply voltages	VDD = 1.8 V, VDDA = 3.3 V, VDDOx = 1.8/2.5/3.3 V - decoupled analog/digital domains minimize supply-induced jitter.

Pinout & Package

SI5341B-B03628-GM is housed in a 64-pin QFN (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5341 Detailed Block Diagram (Figure 2.1) and Register Map documentation.

Pin/Terminal	Circuit Role	Design Meaning
XA/XB	Crytal oscillator input or differential clock input	Primary low-noise reference path; supports 25 MHz crystal or 48–54 MHz TCXO for optimal jitter performance.
IN0/IN1/IN2	Secondary single-ended clock inputs	Provide redundant or auxiliary references; selectable via IN_SEL[1:0] register bits.
OUT0–OUT9	Differential or LVCMOS clock outputs	Each independently configurable for format, amplitude, polarity, and enable; routed via internal crosspoint mux.
VDDO0–VDDO9	Per-output I/O supply pins	Enable mixed-signal board design: e.g., OUT0 at 1.8 V for FPGA bank, OUT3 at 3.3 V for legacy PHY.
RSTb	Active-low hardware reset	Triggers full initialization and NVM reload - required for deterministic power-up state recovery.
INTRb	Open-drain interrupt output	Asserts on loss-of-lock (LOL), loss-of-signal (LOSXAB), or other monitored faults - enables real-time system health monitoring.

Key Features

Feature	Design Value
MultiSynth™ fractional-N synthesis	44-bit numerator / 32-bit denominator resolution enables true any-frequency generation with zero ppm error - eliminates need for multiple discrete oscillators.
Integrated DSPLL with no external loop filter	Reduces BOM count and PCB area while eliminating sensitivity to layout parasitics - improves jitter stability across temperature and voltage.
Per-output VDDO and format selection	Supports simultaneous LVPECL, LVDS, HCSL, CML, and LVCMOS outputs - simplifies interface to heterogeneous ICs without level-shifting components.
Zero-delay mode	Synchronizes output phase to input reference - critical for deterministic latency in packet processing and time-sensitive networking (TSN) applications.
Dynamic frequency update without PLL reset	Enables real-time clock rate adaptation (e.g., for adaptive bitrate video encoding or variable-rate ADC sampling) without output interruption or phase discontinuity.

Applications

5G Radio Unit Timing	High-Speed Data Converter Clocking
Use Scenario: Synchronizing multiple RF transceivers and digital front-end FPGAs in massive MIMO active antenna systems. IC Role / Device Role / Timing Role: Primary clock generator providing phase-aligned 122.88 MHz, 245.76 MHz, and 307.2 MHz outputs to ADC/DACs and JESD204B SerDes lanes. Use Value: Sub-100 fs jitter ensures ENOB preservation in 16-bit+ ADCs; zero-delay mode maintains deterministic inter-device skew under dynamic beamforming changes.	Use Scenario: Driving high-resolution ADCs and DACs in test equipment and medical imaging systems. IC Role / Device Role / Timing Role: Low-phase-noise master clock source delivering synchronized sampling clocks across multiple converter channels. Use Value: 95 fs RMS jitter directly translates to >16.5 effective bits at 125 MSPS; independent VDDO supplies allow direct interface to mixed-voltage converter families.
Optical Transport Network Line Cards	Enterprise Switch ASIC Timing
Use Scenario: Generating OC-192, OTU2, and SyncE-compliant clocks in metro DWDM line cards. IC Role / Device Role / Timing Role: Jitter-clean frequency translator converting 10 MHz or 155.52 MHz reference into multiple SONET/SDH line rates. Use Value: Meets GR-253-CORE mask B (1.5 ps RMS) and ITU-T G.823/G.825 requirements; integrated DCO mode supports EEC Option I/II holdover.	Use Scenario: Providing core, memory, and SerDes clocks to multi-core switch ASICs in 10/25/100 GbE top-of-rack switches. IC Role / Device Role / Timing Role: Centralized clock hub distributing 156.25 MHz (10G), 312.5 MHz (25G), and 625 MHz (100G) clocks with tight inter-output skew. Use Value: Crosspoint routing and per-output R-divider enable exact frequency derivation without external dividers; LVDS/LVPECL compatibility covers all major switch vendor I/O standards.

5G Radio Unit Timing

High-Speed Data Converter Clocking

Use Scenario: Synchronizing multiple RF transceivers and digital front-end FPGAs in massive MIMO active antenna systems.

IC Role / Device Role / Timing Role: Primary clock generator providing phase-aligned 122.88 MHz, 245.76 MHz, and 307.2 MHz outputs to ADC/DACs and JESD204B SerDes lanes.

Use Value: Sub-100 fs jitter ensures ENOB preservation in 16-bit+ ADCs; zero-delay mode maintains deterministic inter-device skew under dynamic beamforming changes.

Use Scenario: Driving high-resolution ADCs and DACs in test equipment and medical imaging systems.

IC Role / Device Role / Timing Role: Low-phase-noise master clock source delivering synchronized sampling clocks across multiple converter channels.

Use Value: 95 fs RMS jitter directly translates to >16.5 effective bits at 125 MSPS; independent VDDO supplies allow direct interface to mixed-voltage converter families.

Optical Transport Network Line Cards

Enterprise Switch ASIC Timing

Use Scenario: Generating OC-192, OTU2, and SyncE-compliant clocks in metro DWDM line cards.

IC Role / Device Role / Timing Role: Jitter-clean frequency translator converting 10 MHz or 155.52 MHz reference into multiple SONET/SDH line rates.

Use Value: Meets GR-253-CORE mask B (1.5 ps RMS) and ITU-T G.823/G.825 requirements; integrated DCO mode supports EEC Option I/II holdover.

Use Scenario: Providing core, memory, and SerDes clocks to multi-core switch ASICs in 10/25/100 GbE top-of-rack switches.

IC Role / Device Role / Timing Role: Centralized clock hub distributing 156.25 MHz (10G), 312.5 MHz (25G), and 625 MHz (100G) clocks with tight inter-output skew.

Use Value: Crosspoint routing and per-output R-divider enable exact frequency derivation without external dividers; LVDS/LVPECL compatibility covers all major switch vendor I/O standards.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5341B-B04229-GM	Factory preprogrammed for 156.25 MHz / 312.5 MHz / 625 MHz outputs; same 64-QFN package and pinout.	Fixed-frequency variant optimized for Ethernet SerDes; lacks full field-programmability of SI5341B-B03628-GM.	Select when requiring guaranteed out-of-box operation for standard data rates without ClockBuilder Pro configuration.
LMK04832RHAT	Two cascaded PLLs, lower max output count (14), higher power consumption (320 mW vs. 240 mW), supports JESD204B subclass 1.	Better suited for ultra-low-latency deterministic clock distribution in radar and instrumentation; less flexible for multi-protocol timing.	Choose when JESD204B subclass 1 deterministic delay or dual-loop jitter cleaning is required - not a drop-in replacement.

Compared with Si5341B-B04229-GM, SI5341B-B03628-GM offers full in-field reprogramming and arbitrary frequency synthesis, while LM K04832RHAT provides superior jitter cleaning in dual-PLL mode but requires more complex layout and power design.

Availability

SI5341B-B03628-GM is available at Aetrix Electronics and suitable for 5G infrastructure, optical transport, high-speed data acquisition, and enterprise switching applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5341B-B03628-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and precision timing expertise.

The Si5341 family was designed to replace complex clock trees in high-performance communications and computing systems, delivering ultra-low jitter, multi-output flexibility, and software-defined configurability in a single IC.

FAQ

What is the primary function of the SI5341B-B03628-GM in a timing architecture?

The SI5341B-B03628-GM serves as an ultra-low-jitter, programmable clock generator that synthesizes up to 10 independent output frequencies from a single reference input. Its MultiSynth™ architecture enables any-frequency generation with zero ppm error, making it ideal for replacing multiple fixed-frequency oscillators in systems like 5G radios and optical line cards. SI5341B-B03628-GM eliminates discrete loop filters and reduces timing BOM complexity while maintaining sub-100 fs jitter performance.

Does the SI5341B-B03628-GM require external loop filter components?

No, the SI5341B-B03628-GM integrates a fully functional DSPLL with on-chip loop filter circuitry. This eliminates the need for external resistors, capacitors, or inductors typically required in traditional PLL designs - reducing PCB area, component count, and sensitivity to layout-induced noise. SI5341B-B03628-GM achieves its specified jitter performance without any external loop compensation elements.

Can the SI5341B-B03628-GM generate different output signal formats simultaneously?

Yes, the SI5341B-B03628-GM supports independent signal format selection per output: LVPECL, LVDS, HCSL, CML, or LVCMOS. Each output has its own VDDO supply pin, allowing mixed-voltage operation - for example, OUT0 configured as 1.8 V LVDS for an FPGA bank while OUT5 operates as 3.3 V LVCMOS for a legacy microcontroller. This capability is enabled by dedicated output driver circuitry and crosspoint routing inside SI5341B-B03628-GM.

How is the SI5341B-B03628-GM programmed and configured?

The SI5341B-B03628-GM is configured via I²C or SPI interface using Skyworks' ClockBuilder Pro software, which calculates optimal divider values and generates register maps. Configuration can be stored in on-chip NVM for power-up operation - SI5341B-B03628-GM supports two field-programmable user NVM banks. Factory preprogramming is also available, but SI5341B-B03628-GM retains full in-circuit reprogrammability throughout its lifetime.

What reference inputs does the SI5341B-B03628-GM support?

The SI5341B-B03628-GM accepts reference inputs from four sources: a crystal (25 MHz or 48–54 MHz) across XA/XB pins, or single-ended clocks on IN0, IN1, or IN2. The XA/XB path features a lower-noise input buffer, making it preferred for high-stability references like TCXOs. Input selection is controlled by the IN_SEL[1:0] register bits, and fault monitoring (LOL, LOSXAB) is available on all paths - a key capability of SI5341B-B03628-GM for redundant timing architectures.

SI5341B-B03628-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 64-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Obsolete

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 64-QFN (9x9)

SI5341B-B03628-GM FAQ

1.How can I place an order for SI5341B-B03628-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5341B-B03628-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5341B-B03628-GM reliable?

The price and inventory of SI5341B-B03628-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5341B-B03628-GM is usually 5 days.

3.What payment methods are accepted for SI5341B-B03628-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5341B-B03628-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5341B-B03628-GM?

SI5341B-B03628-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5341B-B03628-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5341B-B03628-GM?

For technical support, including SI5341B-B03628-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5341B-B03628-GM requirements.

6.How does Aetrix verify that SI5341B-B03628-GM is sourced from the original manufacturer or authorized distributors?

All SI5341B-B03628-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5341B-B03628-GM meets industry standards.

7.What is the process for return or replacement of SI5341B-B03628-GM?

All SI5341B-B03628-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5341B-B03628-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5341B-B03628-GM part is unused and in its original packaging.

Return procedure for SI5341B-B03628-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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