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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5341B-B-GMR

Name: SI5341B-B-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5341B-B-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5341B-B-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 64-VFQFN Exposed Pad

Datasheet:: SI5341B-B-GMR.pdf

Description:: IC CLK BUFFER PLL 64QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5341B-B-GMR from Skyworks Solutions is an ultra-low-jitter, any-frequency clock generator IC with 10 programmable differential/LVCMOS outputs, integrated DSPLL and five independent MultiSynth™ fractional-N dividers, supporting output frequencies from 100 Hz to 712.5 MHz per channel. It powers up with factory- or field-programmed NVM configuration and is used in high-speed networking, telecom infrastructure, and data center timing systems requiring sub-200 fs RMS jitter.

For engineers reviewing the SI5341B-B-GMR datasheet, SI5341B-B-GMR pinout, SI5341B-B-GMR application, or SI5341B-B-GMR equivalent, key selection considerations include its 64-pin QFN package, I²C/SPI programmability, zero-delay mode capability, differential output format flexibility (LVPECL/LVDS/HCSL/CML), and support for crystal or external reference inputs on XA/XB or IN0–IN2.

Technical Context

The SI5341B-B-GMR implements a fully integrated DSPLL architecture with no external loop filter required, locking to reference inputs (25 MHz crystal or 48–54 MHz XTAL, or external clocks on XA/XB/IN0–IN2) and distributing phase-coherent outputs via a crosspoint mux. Its five 44-bit numerator / 32-bit denominator MultiSynth™ N-dividers enable true any-frequency synthesis with 0 ppm frequency error.

Each of the 10 outputs features independent VDDO supply, selectable signal format (LVPECL, LVDS, HCSL, CML, or LVCMOS), programmable amplitude, polarity, and synchronous/asynchronous enable/disable control. The device supports dynamic frequency reconfiguration without PLL relock and includes fault monitoring (LOL, LOSXAB) with interrupt pin (INTRb) and status registers.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	10 independently configurable outputs - enables full clock tree consolidation onto single IC.
RMS jitter (12 kHz–20 MHz)	95 fs typical at 156.25 MHz - meets stringent SerDes and optical module timing requirements.
Output frequency range	100 Hz to 712.5 MHz per output - supports baseband, Ethernet, OTN, CPRI, and PCIe Gen5+ clocks.
Input references	Crystal (XA/XB, 25 MHz or 48–54 MHz) or external clock (XA/XB, IN0–IN2) - dual-path redundancy and flexible sourcing.
Programmability	In-circuit NVM with 2 user banks - allows field updates without reflashing hardware; configures at power-up.
Interface	I²C (up to 400 kHz) and SPI (up to 50 MHz) - supports both embedded host MCU and production programming.
Supply voltages	VDD = 1.8 V, VDDA = 3.3 V, VDDOx = 1.8/2.5/3.3 V per output - enables mixed-signal level translation without external buffers.

Pinout & Package

SI5341B-B-GMR is housed in a thermally enhanced 64-pin QFN (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5341 Rev D Reference Manual (Fig. 2.1) and Si5341B-B-GMR-specific ordering information.

Pin/Terminal	Circuit Role	Design Meaning
RSTb	Active-low hard reset input	Triggers full initialization and NVM reload; functionally identical to power cycle.
OE	Output enable control	Global asynchronous enable/disable; can be asserted per-output via register control.
INTRb	Interrupt output	Open-drain status indicator for LOL (loss of lock), LOSXAB (loss of crystal), or other faults.
SDA/SDIO	I²C data / SPI bidirectional data	Shared pin for I²C (bidirectional) or SPI (data-in/out depending on mode); mode selected by I2C_SEL.
SCLK	Serial clock input	Drives I²C or SPI interface; supports up to 50 MHz SPI clock for fast field programming.
XA/XB	Differential crystal/clock input	Low-noise input path; supports 25 MHz crystal or 48–54 MHz XTAL; internal 8 pF CL, adjustable ±1000 ppm offset.
IN0–IN2	Additional clock inputs	Three single-ended or differential reference inputs; selectable as primary or backup sources via IN_SEL[1:0].
OUT0–OUT9	Differential/LVCMOS clock outputs	10 individually configurable outputs; each with dedicated VDDO, format, amplitude, and phase alignment controls.

Key Features

Feature	Design Value
MultiSynth™ fractional-N synthesis	Five independent 44/32-bit N-dividers enable simultaneous, jitter-optimized generation of up to 10 unrelated frequencies.
Zero-delay mode	Eliminates propagation delay between input reference and selected output - critical for deterministic latency in packet processing.
Integrated DSPLL	Fully on-chip PLL with no external loop filter components - reduces board area, BOM count, and noise coupling risk.
Dynamic reconfiguration	Real-time output frequency changes without PLL unlock/relock - maintains system synchronization during runtime adjustments.
Output crosspoint mux	Arbitrarily routes any synthesized MultiSynth™ frequency to any output driver - maximizes routing flexibility and design reuse.

Applications

5G Radio Unit (RU)	Optical Transport Network (OTN)
Use Scenario: Synchronizing JESD204B ADC/DAC interfaces and FPGA fabric clocks in massive MIMO radio units with strict phase alignment across multiple RF chains. IC Role / Device Role / Timing Role: Primary clock generator providing phase-aligned 245.76 MHz, 491.52 MHz, and 122.88 MHz outputs with <100 fs jitter to meet 3GPP Release 16 fronthaul timing specs. Use Value: Enables deterministic sampling across 64+ antenna elements using single SI5341B-B-GMR, eliminating inter-channel skew and reducing timing calibration overhead.	Use Scenario: Generating line-rate clocks (e.g., 10.709 GHz derived from 155.52 MHz) and client-layer clocks (e.g., 1.25 GHz, 10 GbE) in OTN add-drop multiplexers. IC Role / Device Role / Timing Role: High-stability clock source meeting ITU-T G.8262 EEC-2 compliance with holdover stability <0.01 ppm over temperature. Use Value: Replaces discrete oscillator + divider + buffer chains, reducing jitter accumulation and enabling seamless hitless switching between primary/backup references.
Data Center Switch ASIC	PCIe Gen5/Gen6 Root Complex
Use Scenario: Providing low-jitter reference clocks to multi-terabit switch ASICs requiring synchronized 100/200/400 GbE SerDes lanes and internal memory controllers. IC Role / Device Role / Timing Role: Centralized clock hub delivering 156.25 MHz (Ethernet), 322.265625 MHz (InfiniBand HDR), and 1 GHz (DDR5 PHY) with independent amplitude tuning per domain. Use Value: Achieves <200 fs RMS jitter at 156.25 MHz - exceeds IEEE 802.3cd spec margin and eliminates bit-error-rate degradation in 400G-ZR coherent optics.	Use Scenario: Supplying PCIe reference clocks (100 MHz differential) and auxiliary clocks (e.g., 33 MHz, 48 MHz) to CPU root complexes and CXL-enabled accelerators. IC Role / Device Role / Timing Role: Compliant PCIe Gen5 clock generator with spread-spectrum modulation support and SS disable capability for test modes. Use Value: Meets PCI-SIG® Gen5 clock jitter spec (1.5 ps pk-pk @ 12 kHz–20 MHz) while enabling single-part clocking for CPU, GPU, and NVMe subsystems.

5G Radio Unit (RU)

Optical Transport Network (OTN)

Use Scenario: Synchronizing JESD204B ADC/DAC interfaces and FPGA fabric clocks in massive MIMO radio units with strict phase alignment across multiple RF chains.

IC Role / Device Role / Timing Role: Primary clock generator providing phase-aligned 245.76 MHz, 491.52 MHz, and 122.88 MHz outputs with <100 fs jitter to meet 3GPP Release 16 fronthaul timing specs.

Use Value: Enables deterministic sampling across 64+ antenna elements using single SI5341B-B-GMR, eliminating inter-channel skew and reducing timing calibration overhead.

Use Scenario: Generating line-rate clocks (e.g., 10.709 GHz derived from 155.52 MHz) and client-layer clocks (e.g., 1.25 GHz, 10 GbE) in OTN add-drop multiplexers.

IC Role / Device Role / Timing Role: High-stability clock source meeting ITU-T G.8262 EEC-2 compliance with holdover stability <0.01 ppm over temperature.

Use Value: Replaces discrete oscillator + divider + buffer chains, reducing jitter accumulation and enabling seamless hitless switching between primary/backup references.

Data Center Switch ASIC

PCIe Gen5/Gen6 Root Complex

Use Scenario: Providing low-jitter reference clocks to multi-terabit switch ASICs requiring synchronized 100/200/400 GbE SerDes lanes and internal memory controllers.

IC Role / Device Role / Timing Role: Centralized clock hub delivering 156.25 MHz (Ethernet), 322.265625 MHz (InfiniBand HDR), and 1 GHz (DDR5 PHY) with independent amplitude tuning per domain.

Use Value: Achieves <200 fs RMS jitter at 156.25 MHz - exceeds IEEE 802.3cd spec margin and eliminates bit-error-rate degradation in 400G-ZR coherent optics.

Use Scenario: Supplying PCIe reference clocks (100 MHz differential) and auxiliary clocks (e.g., 33 MHz, 48 MHz) to CPU root complexes and CXL-enabled accelerators.

IC Role / Device Role / Timing Role: Compliant PCIe Gen5 clock generator with spread-spectrum modulation support and SS disable capability for test modes.

Use Value: Meets PCI-SIG® Gen5 clock jitter spec (1.5 ps pk-pk @ 12 kHz–20 MHz) while enabling single-part clocking for CPU, GPU, and NVMe subsystems.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5342B-B-GMR	Same architecture but with 4 outputs instead of 10; shares identical NVM programming flow and ClockBuilder Pro support.	Targeted at cost-sensitive, lower I/O-count applications (e.g., edge routers, small-cell base stations).	Select when only 4 outputs are needed and board space or BOM cost is constrained - same footprint not supported.
LMK04832RHAR	Two-stage PLL (jitter cleaner + generator); higher integrated phase noise floor (>150 fs RMS typical); requires external loop filter.	Better suited for ultra-low-noise cleaning of noisy references rather than pure any-frequency generation.	Choose when input reference has >1 ps jitter and must be cleaned before distribution - SI5341B-B-GMR excels as standalone synthesizer.

Compared with Si5342B-B-GMR, SI5341B-B-GMR provides six additional outputs and full crosspoint routing, making it suitable for complex multi-protocol systems; versus LMK04832RHAR, it eliminates external loop components and delivers superior synthesis flexibility but trades off some jitter cleaning capability.

Availability

SI5341B-B-GMR is available at Aetrix Electronics and suitable for 5G infrastructure, optical transport, data center switching, and high-performance computing applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5341B-B-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and clocking expertise.

The SI5341B-B-GMR belongs to Skyworks' Si534x ultra-low-jitter clock generator family, designed specifically for high-speed serial data links, telecom synchronization, and next-generation compute platforms demanding deterministic, multi-frequency timing.

FAQ

What is the maximum output frequency supported by the SI5341B-B-GMR?

The SI5341B-B-GMR supports output frequencies from 100 Hz up to 712.5 MHz per channel. This range covers common standards including 156.25 MHz (10GbE), 322.265625 MHz (InfiniBand HDR), and 491.52 MHz (5G fronthaul), all while maintaining sub-200 fs RMS jitter performance. The upper limit is defined by the internal VCO and output driver bandwidth, not by the MultiSynth™ divider resolution.

Does the SI5341B-B-GMR require external loop filter components?

No, the SI5341B-B-GMR integrates a fully self-contained DSPLL with on-chip loop filter. This eliminates external passive components, reduces PCB area, avoids noise coupling risks associated with discrete filters, and simplifies layout - a key differentiator versus traditional two-stage PLL clock generators. All loop dynamics are configured via register settings.

How many times can the NVM of the SI5341B-B-GMR be reprogrammed in the field?

The SI5341B-B-GMR contains three NVM banks: one reserved for factory programming and two user-accessible banks. This allows up to two field reprogramming cycles using standard VDD (1.8 V) and VDDA (3.3 V) supplies. Each burn operation is verified via DEVICE_READY polling, and ACTIVE_NVM_BANK register confirms the active bank after successful programming.

Can the SI5341B-B-GMR generate zero-delay outputs?

Yes, the SI5341B-B-GMR supports zero-delay mode, where a selected output replicates the phase and timing of a chosen input reference (e.g., XA/XB or IN0) with minimal propagation delay. This feature is implemented digitally within the crosspoint and output path, enabling deterministic latency for time-sensitive applications like packet timestamping and TSN synchronization.

What output signal formats does the SI5341B-B-GMR support?

The SI5341B-B-GMR supports LVPECL, LVDS, HCSL, CML, and LVCMOS output formats - each configurable per output channel. LVCMOS supports drive strength selection (2 mA to 16 mA), swing control (1.2 V to 3.3 V), and polarity inversion. Differential formats include amplitude tuning (e.g., 350–800 mVpp for LVDS) and termination-aware driver settings to match PCB trace impedance.

SI5341B-B-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 64-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

Type:: -

PLL:: Yes

Input:: LVCMOS, LVDS, LVPECL, Crystal

Output:: CML, HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 4:10

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 350MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 3.47V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 64-QFN (9x9)

SI5341B-B-GMR FAQ

1.How can I place an order for SI5341B-B-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5341B-B-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5341B-B-GMR reliable?

The price and inventory of SI5341B-B-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5341B-B-GMR is usually 5 days.

3.What payment methods are accepted for SI5341B-B-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5341B-B-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5341B-B-GMR?

SI5341B-B-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5341B-B-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5341B-B-GMR?

For technical support, including SI5341B-B-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5341B-B-GMR requirements.

6.How does Aetrix verify that SI5341B-B-GMR is sourced from the original manufacturer or authorized distributors?

All SI5341B-B-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5341B-B-GMR meets industry standards.

7.What is the process for return or replacement of SI5341B-B-GMR?

All SI5341B-B-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5341B-B-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5341B-B-GMR part is unused and in its original packaging.

Return procedure for SI5341B-B-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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