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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5341B-D06006-GMR

Name: SI5341B-D06006-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5341B-D06006-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5341B-D06006-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5341B-D06006-GMR.pdf

Description:: IC CLOCK GENERATOR PLL 64QFN

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Product details

Overview

SI5341B-D06006-GMR from Skyworks Solutions is a 4-input, 10-output any-frequency clock generator with ultra-low 90 fs rms phase jitter, supporting differential output frequencies up to 350 MHz and LVCMOS up to 250 MHz. It integrates a wide-band PLL and MultiSynth™ fractional synthesizer to replace multiple XOs, buffers, and translators in FPGA, Ethernet switch, and OTN processor clock trees.

For engineers reviewing the SI5341B-D06006-GMR datasheet, SI5341B-D06006-GMR pinout, SI5341B-D06006-GMR application, or SI5341B-D06006-GMR equivalent, key selection criteria include its 350 MHz max differential output limit, factory-programmable OTP configuration, I²C/SPI programmability, zero-delay mode support, and 64-QFN 9×9 mm package with independent VDDO supply pins per output.

Technical Context

The SI5341B-D06006-GMR implements a wide-band PLL locked to crystal (25–54 MHz) or differential clock inputs (10–750 MHz), feeding proprietary MultiSynth™ fractional dividers that synthesize frequencies from 100 Hz to 350 MHz on each of ten independently configurable outputs. Its architecture supports glitchless on-the-fly frequency changes and DCO mode with 0.001 ppb resolution.

It features an output crosspoint mux enabling any MultiSynth divider to drive any output, programmable common-mode voltage for LVDS/LVPECL, and selectable termination schemes including AC- or DC-coupled differential and LVCMOS with 1.8/2.5/3.3 V drive. Input selection is controlled via IN_SEL[1:0] pins or register, with status monitoring for loss-of-lock (LOL) and loss-of-signal (LOS) on all inputs.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	10 differential or LVCMOS outputs, each independently configurable
Differential output range	100 Hz to 350 MHz - matches Si5341B frequency synthesis mode limit
Phase jitter (rms)	90 fs - measured over 12 kHz–20 MHz offset, enabling high-speed SerDes compliance
Input options	Crystal (25–54 MHz), differential clock (10–750 MHz), or LVCMOS clock (10–250 MHz)
Supply voltages	VDD = 1.8 V ±5%; VDDA = 3.3 V ±5%; independent VDDO per output (1.8/2.5/3.3 V)
Interface	I²C or SPI serial control with in-circuit programmable OTP NVM for power-up configuration
Operating temp	–40 °C to +85 °C - qualified for industrial embedded and networking equipment

Pinout & Package

SI5341B-D06006-GMR is housed in a 64-pin QFN package measuring 9 mm × 9 mm with 0.5 mm pitch and exposed thermal pad. Pin functions are defined per Skyworks Si5341 64-QFN pinout specification (Document No. Si5341-DS-RevD, Section 9).

Pin/Terminal	Circuit Role	Design Meaning
XA/XB	Crystal oscillator input	Accepts 25–54 MHz fundamental-mode crystal; internal load caps configurable
IN0/IN0b, IN1/IN1b, IN2/IN2b	Differential clock inputs	Support 10–750 MHz differential signals; terminated internally or externally
OUT0–OUT9, OUT0b–OUT9b	Differential clock outputs	Each pair independently configurable as LVDS, LVPECL, CML, HCSL, or LVCMOS
VDDO0–VDDO9	Output driver supply	Independent 1.8/2.5/3.3 V supplies per output enable mixed-voltage clock tree generation
OEb	Output enable control	Active-low global enable; individual outputs can be disabled via register
INTRb	Interrupt output	Open-drain flag indicating LOS/LOL events; maskable per status register
I²C_SEL	Interface mode select	High = I²C; low = SPI (4-wire or 3-wire); enables host interface voltage flexibility
RSTb	Hard reset input	Asynchronous active-low reset restoring NVM configuration and initializing PLL

Key Features

Feature	Design Value
Any-frequency synthesis	Generates integer and non-integer output frequencies from any input source without external components
Zero-delay mode	Enables fixed, minimized input-to-output delay by closing feedback loop externally via FB_IN
Glitchless DCO	Real-time frequency adjustment with 0.001 ppb step resolution and no output glitches
Programmable output format	Per-output selection among LVDS, LVPECL, CML, HCSL, and LVCMOS with amplitude and VCM control
In-circuit OTP programming	Two-time writable non-volatile memory stores custom configuration for immediate power-up operation

Applications

FPGA Clocking	Ethernet Switch Timing
Use Scenario: Providing multiple synchronized clocks to FPGA fabric, transceivers, and memory interfaces in high-speed data acquisition systems. IC Role / Device Role / Timing Role: Central clock tree generator replacing discrete oscillators and fanout buffers; delivers jitter-clean clocks at 100–350 MHz to GTX/GTH transceivers and DDR4 PHYs. Use Value: 90 fs rms jitter ensures <1e-12 BER in 25+ Gbps SerDes links; 10-output flexibility eliminates board-level clock distribution complexity.	Use Scenario: Generating line-rate clocks (e.g., 156.25 MHz, 312.5 MHz) and reference clocks for packet processors and PHYs in 10/25/100GbE switches. IC Role / Device Role / Timing Role: Multi-format clock source supporting both differential (LVDS/LVPECL) and single-ended (LVCMOS) requirements across switch ASICs and PHYs. Use Value: Independent VDDO pins allow simultaneous 1.8 V SerDes refclk and 3.3 V management MCU clock; zero-delay mode stabilizes timing across multi-chip switch fabrics.
OTN Framer Synchronization	Broadcast Video Timing
Use Scenario: Delivering precise, low-jitter clocks to OTN mappers, framers, and FEC engines in optical transport line cards. IC Role / Device Role / Timing Role: Jitter-attenuating clock generator locked to SONET/SDH or SyncE references; supports gapped clock inputs per ITU-T G.8262. Use Value: Sub-100 fs jitter meets stringent OIF CEI-28G-LR jitter specs; LOL/LOS monitoring enables automatic failover to backup reference.	Use Scenario: Generating genlock, pixel, and audio clocks (e.g., 74.25 MHz, 148.5 MHz, 297 MHz) for SDI, HDMI, and IP video encoders/decoders. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer producing SMPTE-compliant rates from a single crystal input. Use Value: Fractional MultiSynth enables exact 74.25 MHz generation from 25 MHz crystal with 0 ppm error; LVCMOS outputs drive video serializer logic directly.

FPGA Clocking

Ethernet Switch Timing

Use Scenario: Providing multiple synchronized clocks to FPGA fabric, transceivers, and memory interfaces in high-speed data acquisition systems.

IC Role / Device Role / Timing Role: Central clock tree generator replacing discrete oscillators and fanout buffers; delivers jitter-clean clocks at 100–350 MHz to GTX/GTH transceivers and DDR4 PHYs.

Use Value: 90 fs rms jitter ensures <1e-12 BER in 25+ Gbps SerDes links; 10-output flexibility eliminates board-level clock distribution complexity.

Use Scenario: Generating line-rate clocks (e.g., 156.25 MHz, 312.5 MHz) and reference clocks for packet processors and PHYs in 10/25/100GbE switches.

IC Role / Device Role / Timing Role: Multi-format clock source supporting both differential (LVDS/LVPECL) and single-ended (LVCMOS) requirements across switch ASICs and PHYs.

Use Value: Independent VDDO pins allow simultaneous 1.8 V SerDes refclk and 3.3 V management MCU clock; zero-delay mode stabilizes timing across multi-chip switch fabrics.

OTN Framer Synchronization

Broadcast Video Timing

Use Scenario: Delivering precise, low-jitter clocks to OTN mappers, framers, and FEC engines in optical transport line cards.

IC Role / Device Role / Timing Role: Jitter-attenuating clock generator locked to SONET/SDH or SyncE references; supports gapped clock inputs per ITU-T G.8262.

Use Value: Sub-100 fs jitter meets stringent OIF CEI-28G-LR jitter specs; LOL/LOS monitoring enables automatic failover to backup reference.

Use Scenario: Generating genlock, pixel, and audio clocks (e.g., 74.25 MHz, 148.5 MHz, 297 MHz) for SDI, HDMI, and IP video encoders/decoders.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer producing SMPTE-compliant rates from a single crystal input.

Use Value: Fractional MultiSynth enables exact 74.25 MHz generation from 25 MHz crystal with 0 ppm error; LVCMOS outputs drive video serializer logic directly.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5341A-D-GM1	Supports full 1028 MHz differential output range vs. SI5341B-D06006-GMR's 350 MHz limit	Suitable for 56G PAM4 SerDes or millimeter-wave RF sampling where >350 MHz outputs required	Select Si5341A-D-GM1 only if design requires outputs above 350 MHz; otherwise SI5341B-D06006-GMR offers optimized cost and power for sub-350 MHz clock trees
LMK04832RHAR	Two-stage jitter cleaner (PLL + DPLL) with integrated LDOs; higher power, larger 64-WQFN package	Better suited for ultra-low-noise instrumentation or radar where sub-50 fs jitter and dual-loop cleaning are mandatory	Choose LMK04832RHAR when system-level jitter budget demands <50 fs; SI5341B-D06006-GMR provides superior integration and lower BOM count for standard telecom/datacom clock trees

Compared with Si5341A-D-GM1, SI5341B-D06006-GMR trades maximum output frequency for tighter jitter performance at mid-range frequencies and reduced layout complexity; versus LMK04832RHAR, it offers higher integration density and simpler power sequencing but lacks dual-loop jitter attenuation.

Availability

SI5341B-D06006-GMR is available at Aetrix Electronics and suitable for FPGA clocking, Ethernet switching, and OTN framer applications requiring stable component supply, long-term lifecycle assurance, and factory-programmable configuration.

Supply support for SI5341B-D06006-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a U.S.-based semiconductor company specializing in analog and mixed-signal connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5341 family is designed as a highly configurable, low-jitter clock generator platform targeting high-speed digital systems including 5G baseband units, cloud networking switches, and broadcast video infrastructure.

FAQ

What is the maximum differential output frequency supported by the SI5341B-D06006-GMR?

The SI5341B-D06006-GMR supports differential output frequencies up to 350 MHz, as defined by its Si5341B ordering grade. This is a hard limit enforced by internal frequency synthesis mode configuration and differs from the Si5341A variant's 1028 MHz capability. The 350 MHz ceiling is sufficient for most 10/25/100GbE, CPRI, and OTN applications while optimizing power and jitter performance.

Does the SI5341B-D06006-GMR require external loop filter components?

No, the SI5341B-D06006-GMR does not require external loop filter components. Its wide-band PLL is fully integrated and self-contained, with all necessary filtering implemented internally. This eliminates external passive components, reduces PCB area, and simplifies design validation-key advantages confirmed in the Si5341/40 Rev D datasheet Section 3.2.

Can the SI5341B-D06006-GMR generate LVCMOS outputs at different voltage levels simultaneously?

Yes, the SI5341B-D06006-GMR supports simultaneous LVCMOS outputs at 1.8 V, 2.5 V, and 3.3 V. Each output has a dedicated VDDO pin, allowing independent supply voltage assignment. This enables direct interfacing with mixed-voltage SoCs, FPGAs, and PHYs without level-shifting-verified in Section 3.5.6 of the datasheet.

How is the SI5341B-D06006-GMR configured for zero-delay mode?

The SI5341B-D06006-GMR enters zero-delay mode by opening the internal feedback path and routing one output (recommended: OUT9) to the FB_IN/FB_INb pins via an AC-coupled differential path. Configuration is performed via register settings that disable internal feedback and enable external loop closure. This cancels internal propagation delays, achieving deterministic, minimal input-to-output latency.

Is factory pre-programming available for the SI5341B-D06006-GMR?

Yes, factory pre-programming is available for the SI5341B-D06006-GMR using Skyworks' ClockBuilder Pro software. Users generate a custom part number (e.g., SI5341B-Dxxxxx-GM) specifying frequency plan, output formats, and features; Skyworks writes the configuration into OTP NVM before shipment. Pre-programmed units boot with clocks immediately active-no host processor or firmware required.

SI5341B-D06006-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5341B-D06006-GMR FAQ

1.How can I place an order for SI5341B-D06006-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5341B-D06006-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5341B-D06006-GMR reliable?

The price and inventory of SI5341B-D06006-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5341B-D06006-GMR is usually 5 days.

3.What payment methods are accepted for SI5341B-D06006-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5341B-D06006-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5341B-D06006-GMR?

SI5341B-D06006-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5341B-D06006-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5341B-D06006-GMR?

For technical support, including SI5341B-D06006-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5341B-D06006-GMR requirements.

6.How does Aetrix verify that SI5341B-D06006-GMR is sourced from the original manufacturer or authorized distributors?

All SI5341B-D06006-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5341B-D06006-GMR meets industry standards.

7.What is the process for return or replacement of SI5341B-D06006-GMR?

All SI5341B-D06006-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5341B-D06006-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5341B-D06006-GMR part is unused and in its original packaging.

Return procedure for SI5341B-D06006-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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