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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5342B-B-GMR

Name: SI5342B-B-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5342B-B-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5342B-B-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 44-VFQFN Exposed Pad

Datasheet:: SI5342B-B-GMR.pdf

Description:: IC CLK BUFFER PLL 44QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5342B-B-GMR from Skyworks is a 4-input, 2-output jitter attenuator/clock multiplier with DSPLL™ and MultiSynth™ architecture, delivering 90 fs rms jitter, programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), and support for SyncE (ITU-T G.8262 EEC Option 1/2) in telecom timing applications.

For engineers reviewing the SI5342B-B-GMR datasheet, SI5342B-B-GMR pinout, SI5342B-B-GMR application, or SI5342B-B-GMR equivalent, this device is selected for high-stability clock synthesis in carrier Ethernet switches, OTN transponders, and 10/40/100G line cards where ultra-low jitter, hitless input switching, and holdover performance are critical design requirements.

Technical Context

The SI5342B-B-GMR implements a fourth-generation DSPLL with fully integrated loop filter and digitally programmable loop bandwidth (0.1 Hz–4 kHz), enabling precise jitter filtering and optimization per application. Its MultiSynth output dividers support both integer and fractional synthesis, allowing any-frequency generation from 100 Hz to 350 MHz on each of two outputs.

It operates across freerun, locked, holdover, and zero-delay modes, with automatic/manual input selection across four differential or LVCMOS inputs (8 kHz–750 MHz), status monitoring (LOS/OOF/LOL), and glitchless on-the-fly frequency changes via I²C/SPI interface with on-chip NVM for power-up configuration.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	2 independent, highly configurable clock outputs
Jitter (rms)	90 fs - meets stringent SyncE EEC Option 1/2 phase noise requirements
Max output frequency	350 MHz - specified for SI5342B variant (integer + fractional synthesis)
Input frequency range	Differential: 8 kHz–750 MHz; LVCMOS: 8 kHz–250 MHz - supports gapped clocks and wide protocol coverage
Jitter attenuation BW	0.1 Hz–4 kHz - digitally programmable for optimal system-level jitter filtering
Supply voltages	VDD = 1.8 V ±5%; VDDA = 3.3 V ±5%; independent output supply pins (1.8/2.5/3.3 V)
Operating temp	–40 °C to +85 °C - qualified for industrial and telecom infrastructure environments

Pinout & Package

SI5342B-B-GMR uses a 44-pin QFN package (7 mm × 7 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev D datasheet Section 9 (Pin Descriptions).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Input clock terminals	Four configurable inputs accepting differential (LVDS/LVPECL/CML/HCSL) or single-ended LVCMOS; IN3 serves as FB_IN in zero-delay mode
OUT0, OUT1	Output clock terminals	Two fully programmable outputs supporting LVDS, LVPECL, LVCMOS, CML, HCSL with adjustable amplitude and common-mode voltage
XA/XB	Crytal oscillator interface	Connects to 25–54 MHz fundamental-mode crystal; internal load caps eliminate external components
SCL/SDA or SCLK/SDIO/CSb	Serial interface	I²C or SPI control interface with in-circuit programmable OTP NVM for persistent configuration
INTRb	Interrupt output	Open-drain status flag indicating LOS, OOF, LOL, or other fault conditions
RSTb	Hardware reset	Active-low asynchronous reset initiating full initialization and NVM reload

Key Features

Feature	Design Value
Hitless input switching	Enables phase-continuous transitions between fractionally related input clocks without output disturbance
Programmable holdover	Uses up to 120 s of historical frequency data with configurable averaging window to minimize phase jump during input failure
DCO mode	Supports fine frequency tuning down to 0.001 ppb step size for precision timing calibration
Glitchless on-the-fly reconfiguration	Allows dynamic output frequency changes without cycle slips or phase discontinuities
Zero-delay mode	Configures IN3 as feedback input to align output phase with selected input reference

Applications

Carrier Ethernet Switches	OTN Transponders
Use Scenario: Synchronous Ethernet (SyncE) distribution across multi-port switch fabric with strict ITU-T G.8262 compliance. IC Role / Device Role / Timing Role: Jitter attenuator and clock multiplier generating clean, phase-aligned 125 MHz and 156.25 MHz clocks from recovered line references. Use Value: 90 fs rms jitter ensures EEC Option 2 compliance; programmable loop bandwidth enables optimized wander filtering for long-haul synchronization.	Use Scenario: Line-card timing in optical transport network equipment requiring dual low-jitter clocks for OTU frame alignment and FEC processing. IC Role / Device Role / Timing Role: Dual-output clock synthesizer deriving 155.52 MHz and 622.08 MHz from a common 10 MHz or 125 MHz reference. Use Value: Two independent outputs eliminate need for external fanout buffers; fractional synthesis supports exact OTU rate derivation without external dividers.
10/40/100G Networking	Broadcast Video Timing
Use Scenario: High-speed SerDes clocking in 100G line cards where deterministic latency and sub-100-fs jitter are mandatory. IC Role / Device Role / Timing Role: Jitter attenuator converting noisy recovered 156.25 MHz or 311.04 MHz clocks into ultra-clean references for PAM4 PHYs. Use Value: 90 fs rms jitter directly supports IEEE 802.3bs 100GBASE-LR4/ER4 specifications; integrated DSPLL eliminates discrete loop filter sensitivity to PCB noise.	Use Scenario: Genlock and frame-synchronized clock generation in SDI video routers and IP-based media gateways. IC Role / Device Role / Timing Role: Dual-output jitter cleaner providing SMPTE ST 2059-2–compliant 27 MHz and 74.25 MHz clocks from GPS-disciplined or atomic references. Use Value: Holdover stability <±0.1 ppm over 24 h enables seamless genlock loss recovery; LVDS outputs drive long backplane traces with minimal skew.

Carrier Ethernet Switches

OTN Transponders

Use Scenario: Synchronous Ethernet (SyncE) distribution across multi-port switch fabric with strict ITU-T G.8262 compliance.

IC Role / Device Role / Timing Role: Jitter attenuator and clock multiplier generating clean, phase-aligned 125 MHz and 156.25 MHz clocks from recovered line references.

Use Value: 90 fs rms jitter ensures EEC Option 2 compliance; programmable loop bandwidth enables optimized wander filtering for long-haul synchronization.

Use Scenario: Line-card timing in optical transport network equipment requiring dual low-jitter clocks for OTU frame alignment and FEC processing.

IC Role / Device Role / Timing Role: Dual-output clock synthesizer deriving 155.52 MHz and 622.08 MHz from a common 10 MHz or 125 MHz reference.

Use Value: Two independent outputs eliminate need for external fanout buffers; fractional synthesis supports exact OTU rate derivation without external dividers.

10/40/100G Networking

Broadcast Video Timing

Use Scenario: High-speed SerDes clocking in 100G line cards where deterministic latency and sub-100-fs jitter are mandatory.

IC Role / Device Role / Timing Role: Jitter attenuator converting noisy recovered 156.25 MHz or 311.04 MHz clocks into ultra-clean references for PAM4 PHYs.

Use Value: 90 fs rms jitter directly supports IEEE 802.3bs 100GBASE-LR4/ER4 specifications; integrated DSPLL eliminates discrete loop filter sensitivity to PCB noise.

Use Scenario: Genlock and frame-synchronized clock generation in SDI video routers and IP-based media gateways.

IC Role / Device Role / Timing Role: Dual-output jitter cleaner providing SMPTE ST 2059-2–compliant 27 MHz and 74.25 MHz clocks from GPS-disciplined or atomic references.

Use Value: Holdover stability <±0.1 ppm over 24 h enables seamless genlock loss recovery; LVDS outputs drive long backplane traces with minimal skew.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SI5342A-B-GMR	Same 44-QFN package and pinout; supports full 100 Hz–1028 MHz output range with integer+fractional synthesis	Broadband frequency agility required (e.g., test equipment); higher max output frequency needed	Select SI5342A-B-GMR when >350 MHz outputs or fractional synthesis at full bandwidth are required
SI5344B-D-GM1	4-output variant in same 44-QFN package; identical 0.001–350 MHz output spec and jitter performance	Systems needing ≥3 independent clocks (e.g., multi-ASIC timing domains) without adding second device	Choose SI5344B-D-GM1 when additional output channels are needed while retaining identical jitter, BW, and footprint

Compared with SI5342B-B-GMR, SI5342A-B-GMR offers wider frequency coverage but same pinout and supply, while SI5344B-D-GM1 adds two extra outputs in identical package-both retain 90 fs jitter and SyncE compliance but address distinct channel-count and frequency-range trade-offs.

Availability

SI5342B-B-GMR is available at Aetrix Electronics and suitable for carrier Ethernet switches, OTN transponders, and 10/40/100G networking equipment requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for telecom infrastructure deployments.

Supply support for SI5342B-B-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications, industrial, and automotive markets.

The Si5342 family is designed specifically for high-performance jitter attenuation and any-frequency clock multiplication in telecom and datacom infrastructure, emphasizing SyncE compliance, holdover resilience, and field-programmable flexibility.

FAQ

What is the maximum output frequency supported by the SI5342B-B-GMR?

The SI5342B-B-GMR supports a maximum output frequency of 350 MHz, as defined in the Skyworks Si5345/44/42 Rev D Ordering Guide for the "B" variant. This specification applies to both differential (LVDS/LVPECL/CML/HCSL) and LVCMOS outputs, and is enabled by integer-only synthesis mode. The SI5342B-B-GMR is not rated for operation above 350 MHz - attempting higher frequencies may violate jitter or stability specifications.

Does the SI5342B-B-GMR support ITU-T G.8262 Synchronous Ethernet compliance?

Yes, the SI5342B-B-GMR meets ITU-T G.8262 EEC Option 1 and Option 2 requirements for synchronous Ethernet equipment clocks. This compliance is achieved through its ultra-low 90 fs rms jitter, programmable DSPLL loop bandwidth (0.1 Hz–4 kHz), and robust holdover performance using averaged historical frequency data - all verified per Skyworks' Si5345/44/42 Rev D datasheet Section 1.

How many input clocks can the SI5342B-B-GMR accept, and what types are supported?

The SI5342B-B-GMR accepts four input clocks (IN0–IN3), each configurable as differential (LVDS, LVPECL, CML, HCSL) or single-ended LVCMOS. Differential inputs operate from 8 kHz to 750 MHz; LVCMOS inputs cover 8 kHz to 250 MHz. All inputs support gapped clock detection and qualification, and automatic/manual switching with hitless capability for fractionally related sources.

What package type and pin count does the SI5342B-B-GMR use?

The SI5342B-B-GMR uses a 44-pin QFN package measuring 7 mm × 7 mm with 0.5 mm pitch and an exposed thermal pad (Moisture Sensitivity Level 3). This matches the Si5344 and Si5342 footprints per Skyworks Package Outline Document (Section 10.2), enabling layout reuse across the family. Pin assignments are documented in Section 9 ("Pin Descriptions") of the Rev D datasheet.

Can the SI5342B-B-GMR be programmed in-circuit, and does it retain configuration after power loss?

Yes, the SI5342B-B-GMR features in-circuit programmable one-time-programmable (OTP) non-volatile memory (NVM). Configuration is written via I²C or SPI interface and persists across power cycles, ensuring the device powers up with a known, validated frequency plan. ClockBuilder Pro™ software from Skyworks simplifies register-level configuration and NVM programming without requiring external programmers.

SI5342B-B-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 44-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

Type:: -

PLL:: Yes

Input:: LVCMOS, LVDS, LVPECL, Crystal

Output:: CML, HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 5:2

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 350MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 3.47V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 44-QFN (7x7)

SI5342B-B-GMR FAQ

1.How can I place an order for SI5342B-B-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5342B-B-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5342B-B-GMR reliable?

The price and inventory of SI5342B-B-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5342B-B-GMR is usually 5 days.

3.What payment methods are accepted for SI5342B-B-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5342B-B-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5342B-B-GMR?

SI5342B-B-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5342B-B-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5342B-B-GMR?

For technical support, including SI5342B-B-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5342B-B-GMR requirements.

6.How does Aetrix verify that SI5342B-B-GMR is sourced from the original manufacturer or authorized distributors?

All SI5342B-B-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5342B-B-GMR meets industry standards.

7.What is the process for return or replacement of SI5342B-B-GMR?

All SI5342B-B-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5342B-B-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5342B-B-GMR part is unused and in its original packaging.

Return procedure for SI5342B-B-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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