Skyworks Solutions Inc. SI5344C-D06599-GM

Overview

SI5344C-D06599-GM from Skyworks is a 4-input, 4-output jitter attenuating clock multiplier with fourth-generation DSPLL™ and MultiSynth™ architecture. It delivers ultra-low 90 fs rms jitter, supports integer-only frequency synthesis up to 1028 MHz (differential), and operates across –40 to +85 °C. It is used in Synchronous Ethernet line cards requiring ITU-T G.8262 EEC Option 1/2 compliance.

For engineers reviewing the SI5344C-D06599-GM datasheet, SI5344C-D06599-GM pinout, SI5344C-D06599-GM application, or SI5344C-D06599-GM equivalent, key selection criteria include jitter performance (90 fs rms), programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), input switching modes (hitless/ramped/glitchless), and support for LVDS/LVPECL/LVCMOS/CML/HCSL output formats with independent supply pins.

Technical Context

The SI5344C-D06599-GM implements a digitally controlled DSPLL with fully integrated loop filter and programmable loop bandwidth (0.1 Hz–4 kHz), enabling precise jitter filtering without external components. Its MultiSynth dividers support integer-only synthesis, and the device includes automatic/manual input clock switching with status monitoring (LOS/OOF/LOL).

It features in-circuit programmable OTP NVM for power-up configuration, I²C/SPI control interface, and configurable outputs with programmable amplitude and common-mode voltage. The device supports free-run, locked, and holdover modes, with ramped holdover exit and DCO mode offering 0.001 ppb step size.

Key Specifications

Pinout & Package

SI5344C-D06599-GM is housed in a 44-pin QFN package (7×7 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5344 Rev D datasheet Section 9 (Pin Descriptions).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Compared with SI5344A-D-GM, SI5344C-D06599-GM trades fractional synthesis capability for lower phase noise floor and deterministic spectral purity; versus LMK04832, it provides full integration (no external loop filter) and tighter jitter spec but less architectural flexibility for cascaded timing trees.

Availability

SI5344C-D06599-GM is available at Aetrix Electronics and suitable for OTN muxponders, Synchronous Ethernet line cards, broadcast video equipment, and test & measurement instruments requiring stable component supply across extended product lifecycles.

Supply support for SI5344C-D06599-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications infrastructure, automotive, and industrial markets.

The Si5344 family is designed specifically for high-performance timing in telecom and datacom systems, delivering ultra-low jitter clock synthesis and robust jitter attenuation in compact, integrated packages.

FAQ

What is the primary function of the SI5344C-D06599-GM in a timing architecture?

The SI5344C-D06599-GM serves as a jitter attenuating clock multiplier that cleans and regenerates timing signals from noisy or unstable references. It uses a fourth-generation DSPLL to suppress input jitter while generating up to four precise, low-jitter output clocks. In systems like SyncE line cards, the SI5344C-D06599-GM ensures output jitter remains below 90 fs rms-meeting ITU-T G.8262 EEC Option 1/2-enabling reliable packet synchronization and minimizing bit errors.

Does the SI5344C-D06599-GM support fractional frequency synthesis?

No, the SI5344C-D06599-GM supports integer-only frequency synthesis, as indicated by the "C" suffix in its ordering part number per Skyworks' Ordering Guide. This eliminates fractional spurs and simplifies configuration for fixed-ratio applications such as 155.52 MHz → 622.08 MHz in SONET/SDH gear. For fractional synthesis, engineers should consider SI5344A-D-GM instead-but the SI5344C-D06599-GM delivers superior spectral purity where integer ratios suffice.

How does the SI5344C-D06599-GM handle loss of input reference?

Upon loss of all valid input clocks, the SI5344C-D06599-GM automatically enters holdover mode, using averaged historical frequency data (up to 120 seconds) stored during prior lock to maintain stable output frequency. The holdover frequency is calculated from a programmable window within that history, minimizing phase disturbance. Output drift in holdover depends solely on the XA/XB crystal stability-so a TCXO is recommended for telecom-grade wander performance. This behavior is fully implemented in the SI5344C-D06599-GM without external logic.

What output signal formats does the SI5344C-D06599-GM support?

The SI5344C-D06599-GM supports LVDS, LVPECL, LVCMOS, CML, and HCSL output formats, with per-output programmability for signal amplitude, common-mode voltage (for differential), and drive strength. Each output has an independent supply pin (VDDO0–VDDO3), allowing mixed-voltage operation-for example, driving 1.8 V LVDS SerDes and 3.3 V legacy logic simultaneously. This flexibility makes the SI5344C-D06599-GM suitable for heterogeneous system interfaces without level-shifting components.

Can the SI5344C-D06599-GM be configured without external hardware?

Yes-the SI5344C-D06599-GM includes in-circuit programmable OTP NVM and supports configuration via I²C or SPI interface using Skyworks' ClockBuilder Pro™ software. Factory preprogrammed units (like SI5344C-D06599-GM) ship with validated configurations ready for immediate deployment. No external programmers or debug probes are needed for field updates; register writes through the serial interface allow runtime reconfiguration of output frequencies, input switching policies, and status monitoring settings-all retained in NVM after power cycle.