Skyworks Solutions Inc. SI5344D-B05193-GM
- Part No.:
- SI5344D-B05193-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- -
- Datasheet:
-
SI5344D-B05193-GM.pdf
- Description:
- IC CLK MULTIPLIER ATTENUATOR
- Quantity:
- Payment:

- Shipping:

Inventory:4,139
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5344D-B05193-GM from Skyworks is a 4-input, 4-output jitter attenuator/clock multiplier based on fourth-generation DSPLL™ and MultiSynth™ architectures. It delivers ultra-low 90 fs rms jitter, supports input frequencies up to 350 MHz (differential), output frequencies up to 350 MHz, and meets ITU-T G.8262 EEC Option 1 & 2 for Synchronous Ethernet. It is used in carrier-grade Ethernet switches requiring hitless clock switching and holdover stability.
For engineers reviewing the SI5344D-B05193-GM datasheet, SI5344D-B05193-GM pinout, SI5344D-B05193-GM application, or SI5344D-B05193-GM equivalent, this page provides verified technical context, pin-level design meaning, real-world application mappings, and validated alternative options for SyncE line card and OTN transponder designs.
Technical Context
The SI5344D-B05193-GM implements a digitally controlled DSPLL with fully integrated loop filter and programmable jitter attenuation bandwidth (0.1 Hz–4 kHz). Its MultiSynth architecture enables integer-only frequency synthesis up to 350 MHz, supporting hitless and ramped input switching between four differential or LVCMOS inputs.
It operates in freerun, locked, holdover, and zero-delay modes, with status monitoring (LOS/OOF/LOL), glitchless DCO mode (0.001 ppb step), and independent output supply pins (1.8 V/2.5 V/3.3 V) for mixed-signal timing integrity in multi-rail systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | 4 independent, configurable outputs with crosspoint routing |
| Jitter (rms) | 90 fs - meets stringent SyncE EEC Option 1/2 phase noise requirements |
| Input range (diff) | 8 kHz–350 MHz - supports SONET/SDH, OTN, and Ethernet reference clocks |
| Output range (diff) | 100 Hz–350 MHz - covers 10G/40G/100G line-rate clocking needs |
| Synthesis mode | Integer-only - eliminates fractional spurs in critical telecom applications |
| DSPLL BW | 0.1 Hz–4 kHz - digitally programmable for optimized jitter/wander trade-off |
| Temp range | –40 °C to +85 °C - qualified for industrial and telecom equipment environments |
Pinout & Package
SI5344D-B05193-GM uses a 44-pin QFN package (7 mm × 7 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Rev D datasheet Section 9 (Pin Descriptions).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN0–IN3 | Differential/LVCMOS input clocks | Four selectable reference inputs; IN3 serves as FB_IN in zero-delay mode |
| OUT0–OUT3 | Configurable differential/LVCMOS outputs | Each supports LVDS/LVPECL/CML/HCSL/LVCMOS with programmable amplitude and common-mode voltage |
| XA/XB | Crytal oscillator terminals | Accepts 25–54 MHz fundamental-mode crystal; internal load caps eliminate external components |
| IN_SEL[1:0] | Manual input selection control | Selects active input (IN0–IN3) via GPIO; default behavior unless register-configured otherwise |
| INTRb | Interrupt output | Open-drain flag for LOS/OOF/LOL events; enables real-time fault monitoring without polling |
| VDD/VDDA | Core/analog power supplies | VDD = 1.8 V ±5%; VDDA = 3.3 V ±5% - strict decoupling required for sub-100-fs jitter |
Key Features
| Feature | Design Value |
|---|---|
| Hitless input switching | Eliminates phase transients when switching between fractionally related inputs (e.g., 155.52 MHz ↔ 622.08 MHz) |
| Programmable holdover window | Up to 120 s of historical frequency data; user-defined averaging window minimizes phase jump on input failure |
| Glitchless DCO mode | 0.001 ppb frequency step resolution enables precise wander compensation in SyncE applications |
| Integrated loop filter | Removes external passive components, reducing board area and noise coupling risk in high-density line cards |
| Status monitoring | Dedicated LOS/OOF/LOL flags via INTRb pin - enables autonomous fault recovery without host processor intervention |
Applications
| OTN Transponders | Carrier Ethernet Switches |
|---|---|
Use Scenario: Line-card timing for 100G OTN muxponders requiring dual-reference redundancy and sub-100-fs jitter. IC Role / Device Role / Timing Role: Jitter attenuator and clock multiplier generating synchronous 156.25 MHz, 311.04 MHz, and 622.08 MHz outputs from OC-192/STM-64 references. Use Value: Meets ITU-T G.709 and G.8262 EEC Option 2 specs while enabling hitless switchover during fiber cut events. | Use Scenario: Central timing engine for multi-port 10G/25G/100G Ethernet switch fabric with SyncE compliance. IC Role / Device Role / Timing Role: Primary clock synthesizer distributing phase-aligned clocks to SERDES, PHYs, and packet processors across multiple ASICs. Use Value: Delivers <90 fs rms jitter and holdover stability <±0.1 ppm over 24 h - satisfies MEF 30.1 and IEEE 1588 boundary clock requirements. |
| Broadcast Video Infrastructure | Test & Measurement Equipment |
Use Scenario: Genlock and frame-sync source in SMPTE ST 2110 IP video routers with multi-format support (HD/4K/8K). IC Role / Device Role / Timing Role: Reference clock conditioner accepting tri-level sync or black burst and generating low-jitter parallel/serial pixel clocks. Use Value: Programmable DSPLL bandwidth suppresses jitter from noisy analog sync sources while preserving long-term stability via crystal reference. | Use Scenario: Clock source in high-resolution oscilloscopes and bit-error-rate testers requiring ultra-low phase noise. IC Role / Device Role / Timing Role: Jitter-cleaned master oscillator feeding ADC/DAC sampling clocks and pattern generator timing engines. Use Value: 90 fs rms jitter enables >12-bit ENOB at 1 GHz sampling rates; integer-only synthesis avoids fractional spurs that corrupt spectral purity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar jitter attenuator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SI5344C-B05192-GM | Same 4-in/4-out integer-only synthesis, but factory preprogrammed for 156.25/311.04/622.08 MHz outputs; no NVM reprogramming capability | Fixed-frequency deployment only; unsuitable for field-reconfigurable systems | Select when production volume justifies custom OTP programming and configuration stability is prioritized over flexibility |
| LMK04832RHAR | 3.1 GHz max output, dual-loop architecture, supports JESD204B deterministic latency; higher power, larger 64-QFN package | Better suited for RF sampling and radar where sub-ps deterministic delay matters more than SyncE compliance | Select when system requires JESD204B subclass 1 support or >350 MHz output frequencies - not drop-in compatible |
Compared with SI5344D-B05193-GM, SI5344C-B05192-GM trades field programmability for lower BOM cost and guaranteed startup configuration, while LMK04832RHAR adds JESD204B features and wider bandwidth at the expense of SyncE certification and footprint size.
Availability
SI5344D-B05193-GM is available at Aetrix Electronics and suitable for OTN transponders, Carrier Ethernet switches, and broadcast video infrastructure requiring stable component supply, long-term lifecycle assurance, and full traceability.
Supply support for SI5344D-B05193-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications, automotive, and industrial markets.
The Si5344 family is designed specifically for high-reliability telecom and networking timing applications, delivering jitter attenuation, holdover resilience, and SyncE compliance in compact QFN packages.
FAQ
What is the maximum differential input frequency supported by the SI5344D-B05193-GM?
The SI5344D-B05193-GM supports differential input frequencies up to 350 MHz, as specified in the Si5344 ordering guide for "D" variants. This limit applies to LVDS, LVPECL, and CML inputs. Exceeding 350 MHz may cause loss of lock or increased jitter; the device does not support 750 MHz inputs like the "A" variant.
Does the SI5344D-B05193-GM include non-volatile memory for configuration storage?
Yes, the SI5344D-B05193-GM includes in-circuit programmable one-time-programmable (OTP) memory. It powers up with a known frequency configuration stored in NVM, eliminating the need for external configuration EEPROM or host initialization. The configuration can be updated in-system using I²C or SPI.
Can the SI5344D-B05193-GM generate 100 MHz and 125 MHz simultaneously on separate outputs?
Yes, the SI5344D-B05193-GM can generate 100 MHz and 125 MHz simultaneously on OUT0 and OUT1. Its MultiSynth architecture and output crosspoint allow independent integer division paths per output, with no shared divider constraints. Both frequencies fall within the 100 Hz–350 MHz differential output range.
Is the SI5344D-B05193-GM compliant with ITU-T G.8262 for Synchronous Ethernet?
Yes, the SI5344D-B05193-GM meets ITU-T G.8262 EEC Option 1 and Option 2 specifications. This compliance is achieved through its ultra-low 90 fs rms jitter, programmable DSPLL bandwidth down to 0.1 Hz, and robust holdover performance using averaged historical frequency data.
What crystal frequency is recommended for optimal jitter performance with the SI5344D-B05193-GM?
A 48 MHz to 54 MHz fundamental-mode crystal is recommended for optimal jitter performance with the SI5344D-B05193-GM. Skyworks specifies this range in the Rev D datasheet to minimize phase noise contribution from the oscillator circuit; crystals outside this range may increase integrated jitter beyond the rated 90 fs rms.
SI5344D-B05193-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- *
- Package/Case:
- -
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Divider/Multiplier:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- -
SI5344D-B05193-GM FAQ
1.How can I place an order for SI5344D-B05193-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5344D-B05193-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5344D-B05193-GM reliable?
The price and inventory of SI5344D-B05193-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5344D-B05193-GM is usually 5 days.
3.What payment methods are accepted for SI5344D-B05193-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5344D-B05193-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5344D-B05193-GM?
SI5344D-B05193-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5344D-B05193-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5344D-B05193-GM?
For technical support, including SI5344D-B05193-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5344D-B05193-GM requirements.
6.How does Aetrix verify that SI5344D-B05193-GM is sourced from the original manufacturer or authorized distributors?
All SI5344D-B05193-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5344D-B05193-GM meets industry standards.
7.What is the process for return or replacement of SI5344D-B05193-GM?
All SI5344D-B05193-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5344D-B05193-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5344D-B05193-GM part is unused and in its original packaging.
Return procedure for SI5344D-B05193-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5344D-B05193-GM Tags
-
CD74HCT4046AM96
Texas Instruments

-
MC14046BDWR2G
onsemi

-
501MILFT
Renesas
-
CD74HC7046AM
Texas Instruments
-
CDCVF2505PWR
Texas Instruments

-
RC19004A100GNL#KB0
Renesas
-
SI5351A-B-GTR
Skyworks Solutions Inc.

-
CY2305SXI-1T
Infineon Technologies

-
570BILFT
Renesas

-
CDCE913PWR
Texas Instruments

-
CY2305SXI-1HT
Infineon Technologies

-
DS1086LU+T
Analog Devices Inc./Maxim Integrated
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

