Skyworks Solutions Inc. SI5345A-B02956-GM
- Part No.:
- SI5345A-B02956-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- -
- Datasheet:
-
SI5345A-B02956-GM.pdf
- Description:
- IC CLK MULTIPLIER ATTENUATOR
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Product details
Overview
SI5345A-B02956-GM from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier featuring fourth-generation DSPLL™ and MultiSynth™ technologies. It delivers ultra-low 90 fs rms jitter, supports differential inputs up to 750 MHz and outputs up to 1028 MHz, and operates in free-run, synchronous, or holdover modes - deployed in OTN transponders and SyncE-compliant carrier Ethernet switches.
For engineers reviewing the SI5345A-B02956-GM datasheet, SI5345A-B02956-GM pinout, SI5345A-B02956-GM application, or SI5345A-B02956-GM equivalent, key selection considerations include its G.8262 EEC Option 1/2 compliance, programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), 64-QFN 9×9 mm package, I²C/SPI configurability, and factory preprogrammed NVM configuration.
Technical Context
The SI5345A-B02956-GM implements a digitally controlled DSPLL with fully integrated loop filter and programmable loop bandwidth (0.1 Hz–4 kHz), enabling precise jitter filtering without external components. Its MultiSynth architecture supports fractional-N synthesis across all 10 outputs, allowing independent integer/fractional division (Nn/Nd) and output R-division for arbitrary frequency generation.
It features hitless input switching between fractionally related clocks, glitchless on-the-fly output frequency changes, and DCO mode with 0.001 ppb step size. Input qualification includes LOS/OOF detection, and status monitoring is provided via INTRb pin and register flags - all operating within –40 to +85 °C with 1.8 V core and 3.3 V analog supply rails.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Jitter (rms) | 90 fs - meets stringent ITU-T G.8262 EEC Option 1 & 2 requirements for SyncE line cards. |
| Input range (diff) | 8 kHz–750 MHz - accepts common telecom references including SONET/SDH, OTN, and Ethernet PHY clocks. |
| Output range (diff) | 100 Hz–1028 MHz - covers 10/40/100 GbE, CPRI, and broadcast video timing needs. |
| Jitter BW control | 0.1 Hz–4 kHz digital setting - enables application-level optimization of jitter cleanup vs. transient response. |
| Supply voltages | VDD = 1.8 V ±5%, VDDA = 3.3 V ±5% - separates digital core and analog PLL domains to minimize noise coupling. |
| Package | 64-QFN 9×9 mm - surface-mount footprint compatible with high-density telecom PCB layouts. |
| Temp range | –40 to +85 °C - qualified for industrial and carrier-grade networking equipment deployment. |
Pinout & Package
The SI5345A-B02956-GM is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5345 Rev D datasheet Section 9 (Pin Descriptions).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN0–IN3 | Differential/single-ended clock inputs | Four configurable inputs supporting hitless switching; IN3 serves as FB_IN in zero-delay mode. |
| OUT0–OUT9 | Programmable clock outputs | 10 independently configurable outputs supporting LVDS/LVPECL/LVCMOS/CML/HCSL with amplitude control. |
| XA/XB | Crytal oscillator terminals | Connects 25–54 MHz fundamental-mode crystal; internal load caps eliminate external components. |
| SCL/SDA | I²C serial interface | Two-wire bus for configuration and status readback; supports hot-plug and in-system programming. |
| INTRb | Interrupt output | Active-low open-drain flag indicating LOS, OOF, LOL, or other fault conditions. |
| RSTb | Hardware reset | Asynchronous active-low pin initiating full initialization and NVM reload. |
Key Features
| Feature | Design Value |
|---|---|
| Any-frequency synthesis | Generates arbitrary output frequencies from any input via fractional-N DSPLL + MultiSynth dividers - eliminates need for multiple discrete oscillators. |
| Integrated loop filter | On-chip analog filter removes external passive components, reducing board area and sensitivity to layout-induced noise. |
| Hitless input switching | Preserves phase continuity when switching between fractionally related inputs - critical for hitless protection switching in telecom networks. |
| Programmable holdover | Stores 120 s of historical lock frequency data and computes averaged holdover value using user-defined window/delay - minimizes phase jump during input failure. |
| DCO mode | Enables fine-grained frequency tuning (0.001 ppb steps) via FINC/FDEC pins or register writes - supports dynamic wander correction in SyncE applications. |
Applications
| OTN Transponders | SyncE Carrier Switches |
|---|---|
Use Scenario: Timing recovery and distribution in 100G/400G OTN muxponders where multiple line-rate clocks (e.g., 9.953 Gbps, 10.3125 Gbps) must be regenerated with sub-100 fs jitter. IC Role / Device Role / Timing Role: Jitter attenuator and multi-output clock multiplier synchronizing to line-side reference while cleaning phase noise from recovered clocks. Use Value: Enables meeting ITU-T G.709 FEC timing masks and reduces bit error rates in coherent optical interfaces. | Use Scenario: Providing traceable, low-jitter clocking for IEEE 1588 PTP grandmasters and SyncE EEC-compliant switch fabrics in mobile backhaul. IC Role / Device Role / Timing Role: Primary timing IC delivering G.8262 EEC Option 1/2 compliant outputs to SERDES, PHYs, and packet processors. Use Value: Eliminates need for external TCXO+PLL combos; single-chip solution meets wander and jitter specs across temperature and aging. |
| Broadcast Video Gear | Test & Measurement |
Use Scenario: Genlock and frame-synchronized clock distribution in 4K/8K video routers and converters requiring SMPTE ST 2059-2 compliance. IC Role / Device Role / Timing Role: Multi-format clock generator producing exact multiples of 27 MHz, 74.25 MHz, and 148.5 MHz from a single reference. Use Value: Supports seamless format switching without frame slips; programmable output swing ensures signal integrity across long BNC traces. | Use Scenario: Reference clock source in high-resolution oscilloscopes and bit-error-rate testers demanding ultra-low phase noise and flexible frequency agility. IC Role / Device Role / Timing Role: Low-jitter programmable oscillator replacing fixed XO banks and analog PLL modules in instrument backplanes. Use Value: Enables rapid reconfiguration of test stimulus frequencies without hardware change; 90 fs jitter supports >60 GHz sampling fidelity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar jitter attenuator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5345B-D-GM | Same 10-output architecture but limited to 0.001–350 MHz output range; integer-only synthesis mode. | Suitable for lower-frequency SyncE or enterprise switching where >350 MHz outputs are unnecessary. | Select when cost sensitivity outweighs wideband flexibility and fractional synthesis is not required. |
| LTC6955IUKG#PBF | Analog Devices 5-output jitter cleaner with 225 fs rms jitter; no on-chip NVM; requires external loop filter. | Used in mixed-signal instrumentation where ultra-low additive jitter matters more than multi-output count or embedded configuration. | Choose when system-level jitter budget allows higher floor and design can accommodate external filter components. |
Compared with Si5345B-D-GM, SI5345A-B02956-GM provides full 1028 MHz output capability and fractional-N synthesis for maximum frequency agility; versus LTC6955IUKG#PBF, it trades slightly higher jitter floor for integrated NVM, 10 outputs, and zero external loop filter - simplifying design and improving reliability in telecom infrastructure.
Availability
SI5345A-B02956-GM is available at Aetrix Electronics and suitable for OTN transponders, SyncE carrier switches, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and factory-trimmed timing performance.
Supply support for SI5345A-B02956-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5345 family is engineered as a high-performance jitter attenuator/clock multiplier platform targeting next-generation telecom infrastructure, specifically designed to replace legacy PLL+XO combinations with single-chip, software-configurable timing.
FAQ
What is the primary function of the SI5345A-B02956-GM in a telecom timing system?
The SI5345A-B02956-GM serves as a jitter-attenuating clock multiplier that cleans phase noise from incoming network references (e.g., SyncE or OTN line clocks) and generates multiple low-jitter output clocks. Its DSPLL architecture locks to degraded inputs while suppressing jitter above its programmable bandwidth - making SI5345A-B02956-GM essential for meeting ITU-T G.8262 EEC compliance in carrier-grade equipment.
Does the SI5345A-B02956-GM require external loop filter components?
No. The SI5345A-B02956-GM integrates the entire DSPLL loop filter on-die, eliminating discrete resistors and capacitors. This reduces PCB area, improves repeatability across manufacturing, and avoids noise coupling paths associated with external passive components - a key differentiator of SI5345A-B02956-GM versus traditional PLL-based clock ICs.
How is the SI5345A-B02956-GM configured and programmed?
The SI5345A-B02956-GM is configured via I²C or SPI interface using Skyworks' ClockBuilder Pro™ software, which auto-generates register maps and validates frequency plans. Configuration is stored in on-chip one-time-programmable (OTP) NVM, so SI5345A-B02956-GM powers up with known settings - no host processor boot-time initialization required.
What does "B02956" indicate in the SI5345A-B02956-GM part number?
"B02956" is Skyworks' custom factory preprogrammed configuration code assigned to this specific SI5345A-B02956-GM device. It denotes a unique frequency plan, output format assignment, and operational mode setup validated in ClockBuilder Pro - meaning SI5345A-B02956-GM ships ready-to-use without field programming for its target application.
Can the SI5345A-B02956-GM operate without an external crystal?
No. The SI5345A-B02956-GM requires a 25–54 MHz fundamental-mode crystal connected to XA/XB pins to serve as the stability reference for free-run and holdover modes. While it accepts external REFCLK on XA/XB, the crystal is mandatory for optimal jitter performance and holdover accuracy - a requirement explicitly defined for SI5345A-B02956-GM in the Rev D datasheet.
SI5345A-B02956-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- *
- Package/Case:
- -
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Divider/Multiplier:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- -
SI5345A-B02956-GM FAQ
1.How can I place an order for SI5345A-B02956-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5345A-B02956-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5345A-B02956-GM reliable?
The price and inventory of SI5345A-B02956-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5345A-B02956-GM is usually 5 days.
3.What payment methods are accepted for SI5345A-B02956-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5345A-B02956-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5345A-B02956-GM?
SI5345A-B02956-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5345A-B02956-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5345A-B02956-GM?
For technical support, including SI5345A-B02956-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5345A-B02956-GM requirements.
6.How does Aetrix verify that SI5345A-B02956-GM is sourced from the original manufacturer or authorized distributors?
All SI5345A-B02956-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5345A-B02956-GM meets industry standards.
7.What is the process for return or replacement of SI5345A-B02956-GM?
All SI5345A-B02956-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5345A-B02956-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5345A-B02956-GM part is unused and in its original packaging.
Return procedure for SI5345A-B02956-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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