Skyworks Solutions Inc. SI5345A-B03269-GM
- Part No.:
- SI5345A-B03269-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- -
- Datasheet:
-
SI5345A-B03269-GM.pdf
- Description:
- IC CLK MULTIPLIER ATTENUATOR
- Quantity:
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Product details
Overview
SI5345A-B03269-GM from Skyworks is a 10-channel, any-frequency jitter attenuator and clock multiplier featuring fourth-generation DSPLL™ and MultiSynth™ architectures. It delivers ultra-low 90 fs rms jitter, supports 4 differential or LVCMOS inputs and 10 programmable outputs (LVDS/LVPECL/LVCMOS/CML/HCSL), and operates across –40 to +85 °C for SyncE-compliant networking line cards.
For engineers reviewing the SI5345A-B03269-GM datasheet, SI5345A-B03269-GM pinout, SI5345A-B03269-GM application, or SI5345A-B03269-GM equivalent, key selection factors include G.8262 EEC Option 1/2 compliance, digitally programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), in-circuit NVM configuration, hitless/ramped/glitchless input switching, and support for gapped clock synchronization in carrier-grade timing systems.
Technical Context
The SI5345A-B03269-GM implements a fourth-generation DSPLL with fully integrated loop filter and digitally programmable loop bandwidth (0.1 Hz–4 kHz), enabling precise jitter filtering and holdover stability. Its MultiSynth architecture provides fractional-N synthesis on all 10 outputs, supporting independent integer/fractional division (Nn/Nd) and output R-division for any-frequency generation from 100 Hz to 1028 MHz.
It features automatic/manual input clock selection across four inputs (IN0–IN3), status monitoring (LOS/OOF/LOL), and three switching modes-hitless (for phase-coherent inputs), ramped (for plesiochronous transitions), and glitchless (±500 ppm pull-in)-all controlled via I²C/SPI interface with factory-programmable OTP memory.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Jitter (rms) | 90 fs rms - meets stringent ITU-T G.8262 EEC Option 1 & 2 requirements for Synchronous Ethernet. |
| Input Range | Differential: 8 kHz–750 MHz; LVCMOS: 8 kHz–250 MHz - supports legacy and high-speed network reference clocks. |
| Output Range | Differential: 100 Hz–1028 MHz; LVCMOS: 100 Hz–250 MHz - covers OTN, Ethernet, and broadcast video frequencies. |
| Jitter BW | 0.1 Hz–4 kHz programmable - enables application-level optimization of jitter attenuation vs. wander rejection. |
| Supply Voltages | VDD = 1.8 V ±5%; VDDA = 3.3 V ±5%; independent output supply pins (1.8/2.5/3.3 V) - ensures signal integrity across mixed-voltage systems. |
| Operating Temp | –40 °C to +85 °C - qualified for industrial and telecom infrastructure environments. |
| Crystal Ref | 25–54 MHz external crystal - integrated load caps eliminate external capacitors and reduce noise coupling. |
Pinout & Package
The SI5345A-B03269-GM is housed in a 64-pin QFN package (9 × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5345 64-QFN pinout specification (Rev D).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN0–IN3 | Differential or LVCMOS input | Accepts primary timing references; supports gapped clock lock and hitless switching between frequency-locked sources. |
| XA/XB | Crytal oscillator terminals | Connects 25–54 MHz fundamental-mode crystal; internal load caps eliminate external components and improve jitter performance. |
| OUT0–OUT9 | Configurable clock outputs | Each independently programmable for format (LVDS/LVPECL/LVCMOS/CML/HCSL), amplitude, common-mode voltage, and enable control. |
| SCL/SDA | I²C serial interface | Two-wire bus for register access, NVM programming, and real-time status monitoring (LOS/OOF/LOL). |
| INTRb | Interrupt output | Active-low open-drain flag signaling loss-of-lock, loss-of-signal, or out-of-frequency conditions. |
| RSTb | Hardware reset | Asynchronous active-low pin initiating full initialization and NVM reload - critical for system recovery and deterministic startup. |
Key Features
| Feature | Design Value |
|---|---|
| Any-frequency synthesis | Generates arbitrary output frequencies from any input using fractional P/N/R dividers - eliminates need for multiple fixed-ratio PLLs. |
| Hitless input switching | Preserves output phase continuity when switching between frequency-locked inputs (e.g., redundant SyncE sources) - avoids packet loss in transport networks. |
| Gapped clock support | Locks to modulated reference clocks with missing cycles (e.g., SONET/SDH framed signals) - enables direct use of network-derived timing without external conditioning. |
| Programmable holdover | Uses 120-second frequency history window to compute stable holdover frequency - minimizes phase jump during input failure in carrier-grade systems. |
| DCO mode | Enables fine frequency tuning (as low as 0.001 ppb step) via FINC/FDEC pins or SPI - supports IEEE 1588 boundary clock calibration and wander compensation. |
Applications
| OTN Muxponders | Carrier Ethernet Switches |
|---|---|
Use Scenario: Aggregating 10G/100G client interfaces into OTN frames with strict jitter and wander limits. IC Role / Device Role / Timing Role: Jitter attenuator and multi-rate clock generator synchronizing OTU2/OTU4 framers, FEC engines, and SerDes lanes. Use Value: Meets ITU-T G.709 and G.8262 EEC Option 2 mask requirements while providing 10 independent low-jitter clocks from a single device. | Use Scenario: Providing traceable, phase-aligned clocks across distributed switch fabric, control plane, and management interfaces. IC Role / Device Role / Timing Role: Primary timing IC delivering SyncE-compliant outputs to PHYs, MACs, and CPU subsystems with holdover resilience. Use Value: Maintains <±50 ppb frequency accuracy during input outage via programmable 120-second holdover averaging - satisfies GR-1244-CORE availability targets. |
| Broadcast Video Timing | Test & Measurement Equipment |
Use Scenario: Genlock and frame-sync distribution in 4K/8K video routers, converters, and IP media gateways. IC Role / Device Role / Timing Role: Master clock synthesizer generating SMPTE ST 2059-2 PTP grandmaster references and parallel pixel clocks. Use Value: 90 fs rms jitter and sub-picosecond phase alignment across 10 outputs ensure zero-frame-drop video transport over IP and SDI. | Use Scenario: Reference clock source in high-resolution oscilloscopes, bit-error-rate testers, and protocol analyzers requiring ultra-low phase noise. IC Role / Device Role / Timing Role: Low-jitter clock multiplier generating clean sampling clocks (e.g., 10 GHz harmonics) from oven-controlled crystal references. Use Value: Integrated DSPLL eliminates discrete loop filter sensitivity to PCB layout, enabling repeatable <100 fs jitter performance across production units. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar jitter attenuator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5345B-D-GM | Same 64-QFN package and pinout; limited to 350 MHz max output frequency (vs. 1028 MHz); integer-only synthesis mode. | Targeted at cost-sensitive SyncE line cards where 100G+ SerDes rates are not required. | Select only if application does not require >350 MHz outputs or fractional-N synthesis for fine frequency resolution. |
| LTC6955IUF#PBF | 5-output jitter cleaner (not multiplier); 22 fs rms jitter; no NVM; requires external loop filter; 40-QFN 6×6 mm. | Used in RF test equipment where ultra-low additive jitter dominates over multi-output flexibility. | Choose when absolute lowest jitter is critical and system can accommodate external filter design and lack of in-field reprogramming. |
Compared with SI5345A-B03269-GM, Si5345B-D-GM trades maximum frequency and synthesis flexibility for lower cost, while LTC6955IUF#PBF offers superior jitter but lacks multi-output configurability, NVM, and integrated loop filtering - making SI5345A-B03269-GM optimal for carrier-class, field-upgradable, multi-protocol timing systems.
Availability
SI5345A-B03269-GM is available at Aetrix Electronics and suitable for OTN muxponders, Carrier Ethernet switches, and broadcast video infrastructure requiring stable component supply, long-term lifecycle support, and guaranteed traceability.
Supply support for SI5345A-B03269-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications, automotive, and industrial markets.
The Si5345 family is engineered for carrier-grade timing applications demanding G.8262 compliance, robust holdover, and flexible any-frequency clock synthesis - targeting next-generation optical transport, 5G fronthaul, and precision test instrumentation.
FAQ
What is the primary function of the SI5345A-B03269-GM in a SyncE-compliant system?
The SI5345A-B03269-GM serves as a jitter attenuator and clock multiplier that meets ITU-T G.8262 EEC Option 1 and 2 specifications. It cleans incoming network timing references, generates up to 10 synchronized low-jitter outputs, and maintains frequency stability during input failures via programmable holdover - ensuring continuous SyncE operation in carrier Ethernet switches and line cards.
Does the SI5345A-B03269-GM support gapped clock inputs, and why is this important?
Yes, the SI5345A-B03269-GM supports gapped clock inputs - it can lock to reference signals with intentionally missing cycles, such as those found in SONET/SDH framed timing. This capability allows direct use of network-derived timing without external gap-fillers, reducing BOM count and improving reliability in optical transport systems where SI5345A-B03269-GM is deployed.
How is the SI5345A-B03269-GM configured, and is external hardware required?
The SI5345A-B03269-GM is configured via I²C or SPI interface using Skyworks' ClockBuilder Pro™ software. It includes in-circuit programmable non-volatile memory (OTP), so SI5345A-B03269-GM powers up with a known configuration without external EEPROM or boot ROM. No external hardware is required for basic operation, though a crystal (25–54 MHz) must be connected to XA/XB.
What are the key differences between SI5345A-B03269-GM and Si5345B-D-GM?
SI5345A-B03269-GM supports full 1028 MHz output range with integer-and-fractional synthesis, while Si5345B-D-GM is limited to 350 MHz and integer-only mode. Both share the same 64-QFN package and pinout, but SI5345A-B03269-GM enables finer frequency resolution and higher-speed SerDes clocking - critical for 100G/400G OTN and Ethernet applications where SI5345A-B03269-GM is specified.
Can the SI5345A-B03269-GM operate without an external crystal?
No - the SI5345A-B03269-GM requires an external 25–54 MHz crystal connected to XA/XB pins to provide the reference for free-run and holdover modes. While it accepts external REFCLK on XA/XB (with PREF divider), the crystal is mandatory for optimal jitter performance and G.8262 compliance; omitting it prevents stable operation in holdover and degrades SI5345A-B03269-GM's jitter specification.
SI5345A-B03269-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- *
- Package/Case:
- -
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Divider/Multiplier:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- -
SI5345A-B03269-GM FAQ
1.How can I place an order for SI5345A-B03269-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5345A-B03269-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5345A-B03269-GM reliable?
The price and inventory of SI5345A-B03269-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5345A-B03269-GM is usually 5 days.
3.What payment methods are accepted for SI5345A-B03269-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5345A-B03269-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5345A-B03269-GM?
SI5345A-B03269-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5345A-B03269-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5345A-B03269-GM?
For technical support, including SI5345A-B03269-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5345A-B03269-GM requirements.
6.How does Aetrix verify that SI5345A-B03269-GM is sourced from the original manufacturer or authorized distributors?
All SI5345A-B03269-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5345A-B03269-GM meets industry standards.
7.What is the process for return or replacement of SI5345A-B03269-GM?
All SI5345A-B03269-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5345A-B03269-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5345A-B03269-GM part is unused and in its original packaging.
Return procedure for SI5345A-B03269-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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