Skyworks Solutions Inc. SI5345A-B04767-GMR

Overview

SI5345A-B04767-GMR from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier featuring fourth-generation DSPLL™ and MultiSynth™ technologies. It delivers ultra-low 90 fs rms jitter, supports differential inputs up to 750 MHz and outputs up to 1028 MHz, and operates in free-run, synchronous, or holdover modes - enabling precise clock synthesis for SyncE-compliant 100 GbE line cards.

For engineers reviewing the SI5345A-B04767-GMR datasheet, SI5345A-B04767-GMR pinout, SI5345A-B04767-GMR application, or SI5345A-B04767-GMR equivalent, key selection considerations include its programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), G.8262 EEC Option 1/2 compliance, 64-QFN 9×9 mm package, I²C/SPI configurability, and factory-programmed NVM configuration for known-power-up behavior.

Technical Context

The SI5345A-B04767-GMR implements a digitally controlled DSPLL architecture with fractional input dividers (P), integer/fractional MultiSynth output dividers (N), and programmable R-division for final output frequency synthesis. Its loop filter is fully integrated, eliminating external components and noise coupling risks.

It supports hitless switching between fractionally related inputs, glitchless transitions across ±500 ppm frequency offsets, and ramped holdover exit using user-selectable slew rates (0.2–40,000 ppm/s). The device uses an internal oscillator driven by a 25–54 MHz crystal to maintain stability in free-run and holdover modes.

Key Specifications

Pinout & Package

The SI5345A-B04767-GMR is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5345 Rev D datasheet Section 9 (Pin Descriptions).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Compared with SI5345A-B04767-GMR, Si5345B-D-GM1 trades output frequency headroom and synthesis flexibility for lower cost, while LTC6957-3 offers simpler integration at the expense of programmability, holdover, and multi-output scalability - making SI5345A-B04767-GMR optimal for complex, carrier-grade timing systems requiring field-upgradable configurations and robust failover.

Availability

SI5345A-B04767-GMR is available at Aetrix Electronics and suitable for OTN muxponders, 100 GbE Synchronous Ethernet line cards, and broadcast video master clock systems requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5345A-B04767-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications infrastructure, automotive, and industrial markets.

The Si5345 family is designed specifically for high-performance timing in carrier-grade networking and broadcast equipment - delivering jitter attenuation, multi-frequency synthesis, and resilient holdover in a single IC.

FAQ

What is the primary function of the SI5345A-B04767-GMR in a telecom timing system?

The SI5345A-B04767-GMR serves as a jitter-attenuating clock multiplier that cleans and regenerates multiple precise clock frequencies from noisy or unstable input references. In telecom systems, it ensures compliance with ITU-T G.8262 EEC standards by reducing input jitter to <90 fs rms while supporting hitless switching and holdover - all critical for maintaining synchronization across 100 GbE and OTN infrastructure. SI5345A-B04767-GMR achieves this using its integrated DSPLL and MultiSynth architecture with factory-programmed NVM.

Does the SI5345A-B04767-GMR require external loop filter components?

No, the SI5345A-B04767-GMR integrates the entire DSPLL loop filter on-chip, eliminating the need for external resistors, capacitors, or inductors. This reduces PCB area, avoids noise coupling from discrete components, and improves repeatability across manufacturing lots. The loop bandwidth remains digitally programmable from 0.1 Hz to 4 kHz without hardware changes - a key advantage over legacy analog PLL solutions. SI5345A-B04767-GMR's monolithic filter design is validated in Skyworks' Rev D datasheet Section 3.2.

How does the SI5345A-B04767-GMR handle loss of input clock signal?

Upon loss of all valid input clocks, the SI5345A-B04767-GMR automatically enters holdover mode using its internal oscillator and averaged historical frequency data. It stores up to 120 seconds of locked-frequency history and calculates a final holdover frequency from a programmable window within that data - minimizing phase disturbance during transition. Output stability then depends on the 25–54 MHz crystal connected to XA/XB. SI5345A-B04767-GMR maintains G.8262-compliant performance for extended periods, with drift governed solely by crystal aging and temperature.

Can the SI5345A-B04767-GMR generate both LVDS and LVCMOS outputs simultaneously?

Yes, the SI5345A-B04767-GMR supports concurrent LVDS, LVPECL, LVCMOS, CML, and HCSL outputs across its 10 channels, with per-output programmable signal amplitude and common-mode voltage. Each output driver is independently configurable via register settings, allowing mixed-logic-family timing distribution on a single board - for example, LVDS for SERDES interfaces and LVCMOS for FPGA configuration clocks. This flexibility is confirmed in the Si5345 Rev D datasheet Section 3.9.2 and Table 5.10.

Is the SI5345A-B04767-GMR preprogrammed, and how is configuration managed?

Yes, SI5345A-B04767-GMR is a factory preprogrammed variant with configuration stored in on-chip non-volatile memory (NVM), ensuring known-frequency power-up behavior without host intervention. Configuration is performed using Skyworks' ClockBuilder Pro™ software, which generates custom part numbers (e.g., SI5345A-B04767-GMR) based on user-defined frequency plans. Field updates remain possible via I²C/SPI, preserving design flexibility while guaranteeing reliable boot-time operation - a requirement for carrier-grade network elements.