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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5345A-B05593-GM

Name: SI5345A-B05593-GM
Brand: Skyworks Solutions Inc.
SKU: SI5345A-B05593-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5345A-B05593-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5345A-B05593-GM.pdf

Description:: IC CLK MULTIPLIER ATTENUATOR

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Product details

Overview

SI5345A-B05593-GM from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier featuring fourth-generation DSPLL™ and MultiSynth™ architectures. It delivers 90 fs rms integrated jitter (12 kHz–20 MHz), supports differential inputs up to 750 MHz and outputs up to 1028 MHz, and operates in free-run, locked, or holdover modes with programmable jitter attenuation bandwidth (0.1 Hz–4 kHz). It is deployed in ITU-T G.8262-compliant Synchronous Ethernet line cards.

For engineers reviewing the SI5345A-B05593-GM datasheet, SI5345A-B05593-GM pinout, SI5345A-B05593-GM application, or SI5345A-B05593-GM equivalent, key selection considerations include its 64-QFN 9×9 mm package, I²C/SPI programmability with on-chip NVM, ultra-low jitter performance under SyncE EEC Option 1/2 compliance, and support for hitless/ramped/glitchless input switching in carrier-grade timing systems.

Technical Context

The SI5345A-B05593-GM implements a digitally controlled DSPLL with fractional input dividers (P), high-resolution MultiSynth output dividers (N), and integer output dividers (R) to generate any output frequency from any input frequency. Its loop filter is fully integrated, eliminating external passive components and associated noise coupling risks.

It supports three operational states: locked mode (phase- and frequency-locked to selected input), holdover mode (averaged historical frequency retention up to 120 s), and freerun mode (crystal-referenced stability). Input qualification includes LOS, OOF, and LOL monitoring, with automatic/manual switching and DCO mode offering 0.001 ppb step resolution.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (rms)	90 fs (12 kHz–20 MHz); meets stringent SyncE EEC Option 1/2 requirements for telecom timing
Input range (diff)	8 kHz–750 MHz; accepts SONET/SDH, OTN, and Ethernet reference clocks without external conditioning
Output range (diff)	100 Hz–1028 MHz; covers all common SerDes, PHY, and FPGA clocking needs across 1G–100G interfaces
Jitter BW	0.1 Hz–4 kHz; digitally programmable to optimize attenuation vs. transient response per application
Supply voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%; independent output supply pins (1.8/2.5/3.3 V) enable mixed-signal board integration
Temp range	–40 °C to +85 °C; qualified for industrial and telecom infrastructure environments
Package	64-QFN, 9×9 mm; surface-mount compatible with standard reflow profiles and thermal management

Pinout & Package

The SI5345A-B05593-GM is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5345 Rev D datasheet Section 9 (Pin Descriptions).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential/single-ended clock inputs	Support automatic/manual selection; IN3 serves as FB_IN in zero-delay mode
OUT0–OUT9	Configurable clock outputs	Programmable format (LVDS/LVPECL/LVCMOS/CML/HCSL), amplitude, and common-mode voltage
XA/XB	Crytal oscillator terminals	Accept 25–54 MHz fundamental-mode crystals; internal load caps eliminate external components
SCL/SDA	I²C serial interface	Two-wire control with address selectable via ADDR pins; supports in-circuit NVM programming
INTRb	Interrupt output	Open-drain flag for LOS/OOF/LOL events; enables real-time fault monitoring without polling

Key Features

Feature	Design Value
Any-frequency synthesis	Generates arbitrary output frequencies from any input using fractional P/N/R dividers-no external PLL required
Hitless input switching	Eliminates phase transients when switching between fractionally related inputs (e.g., 155.52 MHz ↔ 622.08 MHz)
Ramped holdover exit	Linear frequency ramp (0.2–40,000 ppm/s) avoids overshoot during recovery from input failure
DCO mode	0.001 ppb frequency tuning resolution via FINC/FDEC pins or register writes-enables precise wander correction
Integrated loop filter	On-die analog filter removes need for external RC networks, reducing layout sensitivity and BOM count

Applications

OTN Muxponder Timing	SyncE Line Card
Use Scenario: Provides low-jitter clocking for dual-rate (10G/100G) OTN muxponders requiring strict jitter transfer and generation masks per ITU-T G.709. IC Role / Device Role / Timing Role: Jitter attenuator and multi-rate clock multiplier synchronizing client-side and line-side SerDes with independent frequency domains. Use Value: 90 fs rms jitter ensures compliance with OTN PMD layer jitter tolerance while enabling flexible rate adaptation across multiple tributaries.	Use Scenario: Serves as primary timing IC in Carrier Ethernet aggregation switches requiring ITU-T G.8262 EEC Option 1/2 compliance. IC Role / Device Role / Timing Role: Holdover-capable jitter cleaner delivering stable 156.25 MHz and 312.5 MHz clocks to MAC/PHY layers during reference loss. Use Value: Programmable 0.1 Hz loop bandwidth and 120-second holdover history buffer maintain <±0.1 ppm frequency accuracy for >24 hours after input failure.
Broadcast Video Sync	Test & Measurement Clock Source
Use Scenario: Generates SMPTE ST 2059-2–compliant PTP grandmaster clocks and video reference signals (e.g., 27 MHz, 74.25 MHz) in IP-based broadcast infrastructure. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer with sub-100 fs jitter, supporting both genlock and freerun operation from TCXO or GPSDO references. Use Value: Ultra-low jitter preserves eye diagram integrity for 4K/8K video transport over 100GbE, minimizing bit error rates in real-time streaming.	Use Scenario: Used in high-precision signal generators and analyzers requiring ultra-stable, programmable clock sources with minimal phase noise. IC Role / Device Role / Timing Role: Low-noise jitter attenuator generating clean sampling clocks (e.g., 1 GHz, 2.5 GHz) from noisy system references. Use Value: Integrated DSPLL achieves 90 fs rms jitter-enabling ENOB > 12 bits in 10 GS/s ADCs and reducing measurement uncertainty in RF test setups.

OTN Muxponder Timing

SyncE Line Card

Use Scenario: Provides low-jitter clocking for dual-rate (10G/100G) OTN muxponders requiring strict jitter transfer and generation masks per ITU-T G.709.

IC Role / Device Role / Timing Role: Jitter attenuator and multi-rate clock multiplier synchronizing client-side and line-side SerDes with independent frequency domains.

Use Value: 90 fs rms jitter ensures compliance with OTN PMD layer jitter tolerance while enabling flexible rate adaptation across multiple tributaries.

Use Scenario: Serves as primary timing IC in Carrier Ethernet aggregation switches requiring ITU-T G.8262 EEC Option 1/2 compliance.

IC Role / Device Role / Timing Role: Holdover-capable jitter cleaner delivering stable 156.25 MHz and 312.5 MHz clocks to MAC/PHY layers during reference loss.

Use Value: Programmable 0.1 Hz loop bandwidth and 120-second holdover history buffer maintain <±0.1 ppm frequency accuracy for >24 hours after input failure.

Broadcast Video Sync

Test & Measurement Clock Source

Use Scenario: Generates SMPTE ST 2059-2–compliant PTP grandmaster clocks and video reference signals (e.g., 27 MHz, 74.25 MHz) in IP-based broadcast infrastructure.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer with sub-100 fs jitter, supporting both genlock and freerun operation from TCXO or GPSDO references.

Use Value: Ultra-low jitter preserves eye diagram integrity for 4K/8K video transport over 100GbE, minimizing bit error rates in real-time streaming.

Use Scenario: Used in high-precision signal generators and analyzers requiring ultra-stable, programmable clock sources with minimal phase noise.

IC Role / Device Role / Timing Role: Low-noise jitter attenuator generating clean sampling clocks (e.g., 1 GHz, 2.5 GHz) from noisy system references.

Use Value: Integrated DSPLL achieves 90 fs rms jitter-enabling ENOB > 12 bits in 10 GS/s ADCs and reducing measurement uncertainty in RF test setups.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5345B-D-GM	Same 10-output architecture but limited to 350 MHz max output frequency; integer-only synthesis mode	Suitable for sub-10G Ethernet and legacy SDH where >350 MHz clocks are unnecessary	Select when cost optimization is prioritized over wideband frequency flexibility
LTC6957-3	4-output jitter cleaner (not multiplier); fixed 3.3 V supply; no NVM; 110 fs rms jitter	Targeted at simpler, lower-channel-count instrumentation or FPGA clocking-not telecom-grade holdover	Choose for compact, low-power applications lacking SyncE or holdover requirements

Compared with SI5345A-B05593-GM, Si5345B-D-GM trades frequency range and synthesis flexibility for lower unit cost, while LTC6957-3 offers smaller footprint and simpler configuration at the expense of telecom-grade holdover, programmable jitter bandwidth, and 10-channel scalability.

Availability

SI5345A-B05593-GM is available at Aetrix Electronics and suitable for OTN muxponders, Synchronous Ethernet line cards, and broadcast video infrastructure requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5345A-B05593-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications, automotive, and industrial markets.

The SI5345A-B05593-GM belongs to Skyworks' Si5345 family of jitter-attenuating clock multipliers, designed specifically for high-reliability telecom and datacenter timing applications demanding G.8262 compliance, holdover resilience, and any-frequency synthesis.

FAQ

What is the maximum differential input frequency supported by the SI5345A-B05593-GM?

The SI5345A-B05593-GM supports differential input frequencies up to 750 MHz, as specified in the Si5345/44/42 Rev D datasheet Section 1. Features List. This enables direct interfacing with high-speed SerDes reference clocks used in 100G Ethernet, OTN, and CPRI applications without external frequency division or level translation.

Does the SI5345A-B05593-GM include non-volatile memory for configuration storage?

Yes, the SI5345A-B05593-GM integrates in-circuit programmable one-time-programmable (OTP) non-volatile memory. This allows the device to power up with a known, factory- or user-defined frequency configuration without requiring external configuration EEPROM or host processor initialization.

How does the SI5345A-B05593-GM achieve ITU-T G.8262 EEC Option 1 and 2 compliance?

The SI5345A-B05593-GM meets ITU-T G.8262 EEC Option 1 and 2 through its ultra-low 90 fs rms jitter (12 kHz–20 MHz), programmable DSPLL loop bandwidth (0.1 Hz–4 kHz), and robust holdover performance using up to 120 seconds of averaged historical frequency data-ensuring phase and frequency stability during reference loss in SyncE networks.

Can the SI5345A-B05593-GM generate LVCMOS outputs?

Yes, the SI5345A-B05593-GM supports LVCMOS outputs across all 10 channels. Each output can be independently configured for LVCMOS format with programmable signal amplitude, polarity, impedance, and swing-enabling direct connection to FPGAs, microcontrollers, and logic devices operating at 1.8 V, 2.5 V, or 3.3 V.

What is the role of the XA/XB pins on the SI5345A-B05593-GM?

The XA/XB pins on the SI5345A-B05593-GM connect to an external fundamental-mode crystal (25–54 MHz) that serves as the ultra-low-jitter reference for the DSPLL's free-run and holdover modes. Internal loading capacitors eliminate the need for external CL components, simplifying layout and improving noise immunity.

SI5345A-B05593-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5345A-B05593-GM FAQ

1.How can I place an order for SI5345A-B05593-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5345A-B05593-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5345A-B05593-GM reliable?

The price and inventory of SI5345A-B05593-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5345A-B05593-GM is usually 5 days.

3.What payment methods are accepted for SI5345A-B05593-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5345A-B05593-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5345A-B05593-GM?

SI5345A-B05593-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5345A-B05593-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5345A-B05593-GM?

For technical support, including SI5345A-B05593-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5345A-B05593-GM requirements.

6.How does Aetrix verify that SI5345A-B05593-GM is sourced from the original manufacturer or authorized distributors?

All SI5345A-B05593-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5345A-B05593-GM meets industry standards.

7.What is the process for return or replacement of SI5345A-B05593-GM?

All SI5345A-B05593-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5345A-B05593-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5345A-B05593-GM part is unused and in its original packaging.

Return procedure for SI5345A-B05593-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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