Skyworks Solutions Inc. SI5345A-B05666-GM

Overview

SI5345A-B05666-GM from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier featuring fourth-generation DSPLL™ and MultiSynth™ technologies. It delivers ultra-low 90 fs rms jitter, supports differential inputs up to 750 MHz and outputs up to 1028 MHz, and operates in free-run, synchronous, or holdover modes - enabling precise clock synthesis for SyncE-compliant 100 GbE line cards.

For engineers reviewing the SI5345A-B05666-GM datasheet, SI5345A-B05666-GM pinout, SI5345A-B05666-GM application, or SI5345A-B05666-GM equivalent, key selection considerations include its 64-QFN 9×9 mm package, programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), G.8262 EEC Option 1/2 compliance, and factory preprogrammed configuration with integer+fractional synthesis capability.

Technical Context

The SI5345A-B05666-GM implements a digitally controlled DSPLL architecture with fully integrated loop filter and programmable loop bandwidth (0.1 Hz–4 kHz), enabling application-level jitter optimization. Its MultiSynth dividers support both integer and fractional-N synthesis across all 10 outputs, with independent R-divider synchronization and crosspoint routing.

It features hitless input switching for fractionally related clocks, glitchless frequency transitions ±500 ppm, and ramped holdover exit using user-selectable slew rates (0.2–40,000 ppm/s). The device uses an external 25–54 MHz crystal on XA/XB pins for freerun/holdover stability and supports LVDS, LVPECL, LVCMOS, CML, and HCSL output formats with programmable amplitude and common-mode voltage.

Key Specifications

Pinout & Package

The SI5345A-B05666-GM is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5345 Rev D datasheet Section 9 (Pin Descriptions).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator/clock multiplier applications.

Compared with SI5345A-B05666-GM, Si5345B-D-GM sacrifices fractional synthesis and high-frequency capability for cost reduction, while LMK04832RHAR trades integrated crystal support and lower jitter for wider output bandwidth and dual-loop flexibility - making SI5345A-B05666-GM optimal for telecom SyncE where jitter, integration, and factory-programmed reliability are prioritized.

Availability

SI5345A-B05666-GM is available at Aetrix Electronics and suitable for OTN muxponders, 100 GbE line cards, and broadcast video infrastructure requiring stable component supply, guaranteed long-term availability, and preconfigured timing solutions.

Supply support for SI5345A-B05666-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The SI5345A-B05666-GM belongs to Skyworks' Si5345 family of jitter-attenuating clock multipliers, designed specifically for high-reliability telecom and datacom applications demanding G.8262 compliance, ultra-low jitter, and field-upgradable timing configurations.

FAQ

What is the primary function of the SI5345A-B05666-GM in a telecom timing architecture?

The SI5345A-B05666-GM serves as a jitter-attenuating clock multiplier that cleans and regenerates high-frequency reference clocks for synchronization-critical systems. It locks to degraded input clocks (e.g., from packet networks), suppresses jitter using its digitally programmable DSPLL, and generates multiple low-jitter outputs - directly enabling ITU-T G.8262 EEC Option 1/2 compliance in 100 GbE and OTN equipment. Its factory preprogrammed configuration ensures repeatable performance without field configuration.

Does the SI5345A-B05666-GM require external loop filter components?

No, the SI5345A-B05666-GM integrates the entire DSPLL loop filter on-chip, eliminating discrete resistors and capacitors. This removes sensitivity to PCB layout parasitics and board-level noise coupling - a key advantage over traditional PLL-based clock ICs. The loop bandwidth remains digitally programmable from 0.1 Hz to 4 kHz without hardware changes, simplifying design validation and field tuning for different jitter/wander trade-offs.

How does the SI5345A-B05666-GM handle input clock failure in a carrier-grade system?

Upon input clock failure, the SI5345A-B05666-GM automatically enters holdover mode using up to 120 seconds of stored frequency history to compute a stable averaged holdover frequency. Its programmable holdover window and delay settings minimize phase disturbance during transition. When the input recovers, it performs glitchless re-lock using either DSPLL or Fastlock bandwidth - ensuring continuous, phase-continuous timing essential for carrier Ethernet and mobile fronthaul applications.

Can the SI5345A-B05666-GM generate both 156.25 MHz and 312.5 MHz simultaneously from a single 10 MHz reference?

Yes, the SI5345A-B05666-GM can generate 156.25 MHz and 312.5 MHz simultaneously from a 10 MHz input using its independent MultiSynth dividers and crosspoint routing. Each output is configured with unique integer+fractional N-divider values derived from the same DSPLL VCO frequency. ClockBuilder Pro calculates exact divider settings to achieve exact frequencies with zero accumulated error - confirmed in the device's factory-programmed configuration for SI5345A-B05666-GM.

Is the SI5345A-B05666-GM pin-compatible with other Si5345 variants like Si5345A-D-GM?

Yes, the SI5345A-B05666-GM shares the identical 64-QFN 9×9 mm package and pinout with all Si5345A-D-GM variants. All power, ground, I²C, input, output, and crystal pins map identically. Differences lie solely in factory-programmed NVM contents (frequency plan, loop bandwidth, output formats) - not in hardware interface. This allows drop-in replacement for field upgrades or design reuse, provided the target application's frequency and jitter requirements match the preprogrammed configuration.