Skyworks Solutions Inc. SI5345A-B05764-GM
- Part No.:
- SI5345A-B05764-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- -
- Datasheet:
-
SI5345A-B05764-GM.pdf
- Description:
- IC CLK MULTIPLIER ATTENUATOR
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Product details
Overview
SI5345A-B05764-GM from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier featuring fourth-generation DSPLL™ and MultiSynth™ architectures. It delivers ultra-low 90 fs rms jitter, supports differential inputs up to 750 MHz and outputs up to 1028 MHz, and operates in free-run, locked, or holdover modes - deployed in OTN transponders and SyncE-compliant carrier Ethernet switches.
For engineers reviewing the SI5345A-B05764-GM datasheet, SI5345A-B05764-GM pinout, SI5345A-B05764-GM application, or SI5345A-B05764-GM equivalent, key selection considerations include jitter attenuation bandwidth programmability (0.1 Hz–4 kHz), G.8262 EEC Option 1/2 compliance, hitless input switching capability, and factory preprogrammed NVM configuration for known-power-up frequency behavior.
Technical Context
The SI5345A-B05764-GM implements a digitally controlled DSPLL with fully integrated loop filter and programmable loop bandwidth (0.1 Hz–4 kHz), enabling precise jitter filtering tailored to application-specific noise profiles. Its MultiSynth architecture supports fractional-N synthesis across all 10 outputs, allowing independent generation of any output frequency from any input frequency within specified ranges.
It features automatic/manual input clock selection across four inputs (IN0–IN3), status monitoring (LOS/OOF/LOL), glitchless on-the-fly frequency changes, and DCO mode with 0.001 ppb step resolution. Core supply is 1.8 V ±5% (VDD), analog supply 3.3 V ±5% (VDDA), with independent output supply pins supporting 1.8 V/2.5 V/3.3 V levels.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Jitter (rms) | 90 fs - meets stringent SyncE EEC Option 1/2 requirements for telecom timing distribution |
| Input range (diff) | 8 kHz–750 MHz - supports SONET/SDH, OTN, and high-speed SerDes reference clocks |
| Output range (diff) | 100 Hz–1028 MHz - covers Ethernet PHYs, FPGA transceivers, and processor clocks |
| Jitter BW control | 0.1 Hz–4 kHz digital programming - enables optimization for wander vs. jitter trade-offs |
| DSPLL modes | Free-run, locked, holdover - ensures continuous timing during input failure or loss-of-signal |
| Output count | 10 configurable outputs - supports multi-domain clocking in line cards and muxponders |
| Supply voltages | VDD = 1.8 V ±5%, VDDA = 3.3 V ±5% - separates digital/analog domains for noise isolation |
Pinout & Package
SI5345A-B05764-GM is housed in a 64-QFN package (9×9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5345 Rev D datasheet Section 9 (Pin Descriptions).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN0–IN3 | Differential/single-ended clock inputs | Support hitless/ramped/glitchless switching; IN3 serves as FB_IN in zero-delay mode |
| OUT0–OUT9 | Programmable clock outputs | Configurable for LVDS/LVPECL/LVCMOS/CML/HCSL with amplitude and common-mode control |
| XA/XB | Crytal oscillator terminals | Accept 25–54 MHz fundamental-mode crystal; internal load caps eliminate external components |
| SCL/SDA | I²C serial interface | Used for configuration, status readback, and NVM programming; supports hot-plug operation |
| INTRb | Interrupt output | Asserts on LOS/OOF/LOL events; enables real-time fault monitoring without polling |
| RSTb | Hardware reset | Initiates hard reset restoring NVM configuration; synchronous with internal clock domain |
Key Features
| Feature | Design Value |
|---|---|
| Any-frequency synthesis | Generates arbitrary output frequencies from any input via fractional-N MultiSynth dividers (Nn/Nd) and input dividers (Pn/Pd) |
| Hitless input switching | Eliminates phase transients when switching between fractionally related inputs (e.g., 155.52 MHz ↔ 622.08 MHz) |
| Programmable holdover | Uses 120-second frequency history window to compute stable holdover frequency after input failure |
| Fastlock acquisition | Temporarily raises loop bandwidth (100 Hz–4 kHz) to reduce lock time without compromising steady-state jitter |
| DCO mode | Enables fine frequency tuning (0.001 ppb steps) via FINC/FDEC pins or register writes during free-run or locked operation |
Applications
| OTN Muxponder Timing | SyncE Carrier Ethernet Switch |
|---|---|
Use Scenario: Provides low-jitter clocking for multiple 100G/400G OTN framers and FEC engines in compact line cards. IC Role / Device Role / Timing Role: Jitter attenuator and frequency translator synchronizing client-side OTU interfaces to line-side DWDM wavelengths. Use Value: 90 fs rms jitter ensures BER <1e-15 in coherent optical receivers; programmable jitter BW suppresses packet-based wander from upstream routers. | Use Scenario: Serves as primary timing source for distributed switching fabric with IEEE 1588 PTP grandmaster and SyncE EEC compliance. IC Role / Device Role / Timing Role: G.8262-compliant clock multiplier generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for MAC, PHY, and CPU domains. Use Value: Meets EEC Option 2 wander limits (<4.6 ppm over 1 s); holdover stability <±0.1 ppm over 24 h using 50 MHz TCXO on XA/XB. |
| Broadcast Video Master Clock | Test & Measurement Reference |
Use Scenario: Generates synchronized SMPTE ST 2059-2 compliant clocks across camera ingest, processing, and playout subsystems. IC Role / Device Role / Timing Role: Multi-output jitter cleaner distributing 27 MHz, 74.25 MHz, and 148.5 MHz video clocks with sub-picosecond phase alignment. Use Value: Ultra-low 90 fs jitter prevents frame sync errors and lip-sync drift; zero-delay mode enables deterministic latency for genlock applications. | Use Scenario: Supplies ultra-stable reference clocks to high-resolution oscilloscopes, bit-error-rate testers, and signal analyzers. IC Role / Device Role / Timing Role: Low-phase-noise clock source with programmable outputs matching instrument-specific sampling rates (e.g., 1 GHz, 500 MHz, 122.88 MHz). Use Value: Integrated DSPLL eliminates discrete loop filter sensitivity to PCB layout; factory preprogramming ensures repeatable calibration-grade timing behavior. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar jitter attenuator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5345B-D-GM | Same 64-QFN package and DSPLL architecture, but limited to 350 MHz max output frequency and no fractional synthesis support | Suitable for lower-speed Ethernet (GbE/10GbE) and legacy SDH where >350 MHz outputs are unnecessary | Select when cost sensitivity outweighs need for 1028 MHz outputs or fractional-N flexibility |
| LMK04832RHAR | TI dual-loop jitter cleaner with 3.1 GHz max output, but higher typical jitter (110 fs rms) and no integrated crystal oscillator | Preferred in RF test equipment requiring >1 GHz outputs and external OCXO integration | Choose when system-level jitter budget allows >20 fs margin or when external ultra-stable reference is already present |
Compared with SI5345A-B05764-GM, Si5345B-D-GM sacrifices frequency range and synthesis flexibility for lower unit cost, while LMK04832RHAR trades jitter performance and integrated crystal support for wider output bandwidth and dual-loop redundancy - making SI5345A-B05764-GM optimal for telecom infrastructure demanding both ultra-low jitter and factory-configured reliability.
Availability
SI5345A-B05764-GM is available at Aetrix Electronics and suitable for OTN transponders, SyncE carrier switches, broadcast video systems, and test equipment requiring stable component supply with guaranteed long-term lifecycle support.
Supply support for SI5345A-B05764-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5345 family is designed specifically for high-reliability telecom and datacom timing applications requiring G.8262 compliance, ultra-low jitter, and robust holdover performance - targeting OTN, SyncE, and broadcast infrastructure.
FAQ
What is the primary function of the SI5345A-B05764-GM in a telecom timing system?
The SI5345A-B05764-GM serves as a jitter attenuating clock multiplier that cleans and regenerates high-frequency reference clocks for OTN, SyncE, and SDH systems. It reduces incoming jitter to 90 fs rms while generating up to 10 independent output frequencies - ensuring phase coherence and meeting ITU-T G.8262 EEC Option 1/2 requirements. Its holdover capability maintains timing integrity during input failures, making SI5345A-B05764-GM critical for carrier-grade network resilience.
Does the SI5345A-B05764-GM require an external crystal, and what is the supported frequency range?
Yes, the SI5345A-B05764-GM requires an external crystal connected to XA/XB pins for free-run and holdover operation. It supports crystals from 25 MHz to 54 MHz, with Skyworks recommending 48–54 MHz for optimal jitter performance. Internal loading capacitors eliminate the need for external C-L components, simplifying layout and reducing noise coupling. The SI5345A-B05764-GM also accepts external REFCLK inputs if a TCXO or OCXO is preferred for enhanced holdover stability.
How does the SI5345A-B05764-GM handle input clock failures, and what is its holdover behavior?
Upon input clock failure, the SI5345A-B05764-GM automatically enters holdover mode using up to 120 seconds of stored frequency history to compute a stable averaged holdover frequency. This minimizes phase disturbance during transitions. Holdover stability depends on the external crystal or TCXO connected to XA/XB - with a 50 MHz TCXO enabling <±0.1 ppm drift over 24 hours. The SI5345A-B05764-GM exits holdover glitchlessly when a valid input returns, optionally ramping output frequency to avoid transients.
Can the SI5345A-B05764-GM generate different output formats on its 10 channels simultaneously?
Yes, the SI5345A-B05764-GM supports independent configuration of each of its 10 outputs for LVDS, LVPECL, LVCMOS, CML, or HCSL signaling, with programmable amplitude and common-mode voltage. This allows simultaneous generation of, for example, 156.25 MHz LVPECL for SerDes, 125 MHz LVDS for PHY interfaces, and 27 MHz LVCMOS for microcontroller peripherals - all from a single SI5345A-B05764-GM device without external level-shifting circuitry.
Is the SI5345A-B05764-GM preprogrammed, and how is configuration managed?
Yes, SI5345A-B05764-GM is a factory preprogrammed part - the "B05764" suffix indicates a specific ClockBuilder Pro-generated configuration stored in on-chip OTP NVM. It powers up immediately with defined input/output mappings, frequencies, and operational modes. Configuration can be updated in-circuit via I²C or SPI, and revised settings can be saved back to NVM. Skyworks' ClockBuilder Pro software is required for custom reconfiguration of the SI5345A-B05764-GM.
SI5345A-B05764-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- *
- Package/Case:
- -
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Divider/Multiplier:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- -
SI5345A-B05764-GM FAQ
1.How can I place an order for SI5345A-B05764-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5345A-B05764-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5345A-B05764-GM reliable?
The price and inventory of SI5345A-B05764-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5345A-B05764-GM is usually 5 days.
3.What payment methods are accepted for SI5345A-B05764-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5345A-B05764-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5345A-B05764-GM?
SI5345A-B05764-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5345A-B05764-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5345A-B05764-GM?
For technical support, including SI5345A-B05764-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5345A-B05764-GM requirements.
6.How does Aetrix verify that SI5345A-B05764-GM is sourced from the original manufacturer or authorized distributors?
All SI5345A-B05764-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5345A-B05764-GM meets industry standards.
7.What is the process for return or replacement of SI5345A-B05764-GM?
All SI5345A-B05764-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5345A-B05764-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5345A-B05764-GM part is unused and in its original packaging.
Return procedure for SI5345A-B05764-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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