Skyworks Solutions Inc. SI5345A-B05764-GMR

Overview

SI5345A-B05764-GMR from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier with fourth-generation DSPLL™ and MultiSynth™ architecture. It delivers 90 fs RMS jitter, supports differential inputs up to 750 MHz and outputs up to 1028 MHz, and operates in free-run, locked, or holdover modes - deployed in OTN transponders and SyncE-compliant carrier Ethernet switches.

For engineers reviewing the SI5345A-B05764-GMR datasheet, SI5345A-B05764-GMR pinout, SI5345A-B05764-GMR application, or SI5345A-B05764-GMR equivalent, key selection criteria include its G.8262 EEC Option 1/2 compliance, programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), hitless input switching capability, and factory-programmed configuration for immediate deployment without external NVM programming.

Technical Context

The SI5345A-B05764-GMR implements a digitally controlled DSPLL with fully integrated loop filter and fractional-N synthesis, enabling ultra-low-jitter clock generation from arbitrary input frequencies. Its architecture includes four configurable inputs (IN0–IN3), ten independently programmable outputs (OUT0–OUT9), and on-chip crystal oscillator (25–54 MHz XA/XB) for freerun/holdover stability.

It supports three operational modes - locked (phase-locked to selected input), freerun (crystal-referenced), and holdover (averaged historical frequency retention up to 120 s) - with glitchless, ramped, and hitless input switching options. The device uses I²C/SPI interface and stores configuration in on-chip OTP NVM, ensuring deterministic power-up behavior.

Key Specifications

Pinout & Package

SI5345A-B05764-GMR is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5345 Rev D datasheet Section 9 (Pin Descriptions).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Compared with SI5345A-B05764-GMR, Si5345B-D-GM1 sacrifices frequency flexibility and jitter performance for cost reduction, while LMK04832 offers broader bandwidth at higher power and complexity - making SI5345A-B05764-GMR optimal for telecom-grade SyncE and OTN where 90 fs and G.8262 compliance are non-negotiable.

Availability

SI5345A-B05764-GMR is available at Aetrix Electronics and suitable for OTN transponders, SyncE carrier switches, broadcast video infrastructure, and test equipment requiring stable component supply with guaranteed long-term lifecycle support.

Supply support for SI5345A-B05764-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5345 family is engineered for high-performance timing in telecom infrastructure, delivering jitter-attenuated, multi-output clock synthesis with deterministic holdover and seamless input switching for mission-critical networks.

FAQ

What is the primary function of the SI5345A-B05764-GMR in a telecom timing system?

The SI5345A-B05764-GMR serves as a jitter-attenuating clock multiplier that cleans and distributes ultra-low-jitter timing signals across multiple subsystems. In telecom applications, it locks to a degraded reference (e.g., recovered OTN clock), suppresses jitter using its DSPLL, and generates synchronized, G.8262-compliant outputs for SerDes, framers, and PHYs - ensuring SI5345A-B05764-GMR maintains sub-100 fs RMS jitter even under stressed input conditions.

Does the SI5345A-B05764-GMR require external loop filter components?

No, the SI5345A-B05764-GMR integrates the entire DSPLL loop filter on-die, eliminating discrete capacitors and resistors. This removes layout sensitivity and noise coupling risks associated with external passive components - a key advantage over legacy PLL designs. All loop dynamics, including bandwidth (0.1 Hz–4 kHz), are configured digitally via the SI5345A-B05764-GMR's I²C/SPI interface.

How does the SI5345A-B05764-GMR handle loss of input clock in a SyncE deployment?

Upon input failure, the SI5345A-B05764-GMR automatically enters holdover mode, using up to 120 seconds of stored frequency history to compute an averaged holdover frequency. This minimizes phase disturbance at outputs. The SI5345A-B05764-GMR sustains G.8262 EEC Option 1/2 compliance during holdover when paired with a TCXO on XA/XB - a behavior confirmed in Skyworks' SyncE validation reports for SI5345A-B05764-GMR.

Can the SI5345A-B05764-GMR generate both LVDS and LVCMOS outputs simultaneously?

Yes, the SI5345A-B05764-GMR supports concurrent LVDS, LVPECL, LVCMOS, CML, and HCSL outputs across its ten channels. Each output is independently configurable for format, amplitude, common-mode voltage (differential), and slew rate (LVCMOS). This flexibility allows SI5345A-B05764-GMR to drive heterogeneous loads - e.g., FPGA banks (LVCMOS), SerDes (LVDS), and RF ICs (CML) - from a single device.

Is the SI5345A-B05764-GMR preprogrammed, and how is its configuration managed?

Yes, SI5345A-B05764-GMR is a factory preprogrammed variant - its configuration (input/output frequencies, formats, modes) is stored in on-chip OTP NVM and loads automatically at power-up. Configuration is generated using Skyworks ClockBuilder Pro™ software and assigned a unique OPN suffix (e.g., "B05764"). No runtime programming is required unless reconfiguration is needed - in which case SI5345A-B05764-GMR supports in-circuit I²C/SPI updates.