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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5345A-B05765-GM

Name: SI5345A-B05765-GM
Brand: Skyworks Solutions Inc.
SKU: SI5345A-B05765-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5345A-B05765-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5345A-B05765-GM.pdf

Description:: IC CLK MULTIPLIER ATTENUATOR

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Product details

Overview

SI5345A-B05765-GM from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier featuring fourth-generation DSPLL™ and MultiSynth™ architectures. It delivers ultra-low 90 fs rms jitter, supports 4 differential or LVCMOS inputs and 10 programmable outputs (LVDS/LVPECL/LVCMOS/CML/HCSL), and operates across –40 to +85 °C. It is deployed in ITU-T G.8262 SyncE-compliant carrier Ethernet switches and OTN transponders requiring deterministic phase alignment and holdover stability.

For engineers reviewing the SI5345A-B05765-GM datasheet, SI5345A-B05765-GM pinout, SI5345A-B05765-GM application, or SI5345A-B05765-GM equivalent, key selection considerations include its digitally programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), hitless input switching capability between fractionally related clocks, DCO mode with 0.001 ppb step size, and factory preprogrammed NVM configuration for guaranteed power-up frequency integrity.

Technical Context

The SI5345A-B05765-GM implements a fourth-generation DSPLL with integrated loop filter and digitally configurable loop bandwidth (0.1 Hz–4 kHz), enabling precise jitter filtering without external components. Its MultiSynth architecture uses fractional-N synthesis (Mn/Md) and integer output division (R) to generate any output frequency from any input-supporting both integer and fractional synthesis modes per channel.

It features automatic and manual input clock selection across four inputs (IN0–IN3), status monitoring (LOS/OOF/LOL), glitchless on-the-fly output frequency changes, and ramped holdover exit with user-selectable slew rates (0.2–40,000 ppm/s). The device operates in freerun, locked, holdover, and zero-delay modes, with full support for gapped clock synchronization and DCO control via FINC/FDEC pins or serial interface.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (rms)	90 fs - meets stringent ITU-T G.8262 EEC Option 1/2 requirements for SyncE line cards.
Input range	Differential: 8 kHz–750 MHz; LVCMOS: 8 kHz–250 MHz - accommodates telecom reference clocks, recovered data clocks, and system oscillators.
Output range	Differential: 100 Hz–1028 MHz; LVCMOS: 100 Hz–250 MHz - covers 10/40/100 GbE, OTN, and broadcast video timing needs.
Jitter BW	0.1 Hz–4 kHz - digitally selectable to optimize attenuation vs. transient response for specific network layer requirements.
Supply voltages	VDD = 1.8 V ±5%; VDDA = 3.3 V ±5%; independent output supplies (1.8/2.5/3.3 V) - enables mixed-signal board integration with noise isolation.
Package	64-QFN, 9×9 mm - surface-mount compatible with high-density telecom PCB layouts and thermal management via exposed pad.
Temp range	–40 to +85 °C - qualified for industrial and carrier-grade networking equipment operating in uncontrolled environments.

Pinout & Package

SI5345A-B05765-GM is housed in a 64-pin QFN package (9×9 mm, 0.5 mm pitch) with an exposed thermal pad. Pin functions are validated per Skyworks Si5345 Rev D datasheet Section 9 (Pin Descriptions) and Figure 10.1 (Package Diagram).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential or LVCMOS input clock terminals	Support automatic/manual selection; tolerate gapped clocks; enable hitless switching when frequencies are fractionally related.
OUT0–OUT9	Configurable differential/LVCMOS output drivers	Each independently programmable for format (LVDS/LVPECL/etc.), amplitude, common-mode voltage, and enable/disable control.
XA/XB	Crystal oscillator input pair	Accepts 25–54 MHz fundamental-mode crystals; internal load caps eliminate external components; critical for holdover stability.
SCL/SDA	I²C serial interface	Two-wire bus for configuration, status readback, and NVM programming; supports hot-plug reconfiguration without reset.
INTRb	Interrupt output	Active-low open-drain flag signaling LOS/OOF/LOL events; enables real-time fault monitoring in carrier systems.
RSTb	Hardware reset input	Asynchronous active-low pin forcing hard reset: reloads NVM defaults and reinitializes all PLLs and dividers.

Key Features

Feature	Design Value
Hitless input switching	Eliminates phase transients during clock source switchover between fractionally related inputs (e.g., 155.52 MHz ↔ 622.08 MHz), preserving SONET/SDH frame alignment.
Programmable holdover window	Stores up to 120 s of historical frequency data; calculates final holdover frequency from a user-defined time window to minimize phase jump upon input failure.
DCO mode with 0.001 ppb resolution	Enables fine-grained frequency tuning for packet network timing recovery (e.g., IEEE 1588 PTP slave clock adjustment) without recalculating full MultiSynth dividers.
Glitchless on-the-fly output changes	Allows dynamic reconfiguration of output frequencies (e.g., switching from 10.7 Gbps SerDes reference to 25.78125 GHz) while maintaining continuous clock output and phase continuity.
Integrated loop filter	Removes need for external RC networks, reducing BOM count, layout sensitivity, and susceptibility to board-level noise coupling in high-speed backplanes.

Applications

OTN Muxponder Timing	SyncE Carrier Ethernet Switch
Use Scenario: Generating synchronized 10.709 GHz, 12.890625 GHz, and 25.78125 GHz SerDes references from a single recovered 155.52 MHz or 622.08 MHz line clock in metro OTN muxponders. IC Role / Device Role / Timing Role: Jitter attenuator and multi-frequency clock multiplier ensuring sub-100 fs rms jitter at all SerDes lanes to meet OTU-4 BER requirements. Use Value: Enables single-chip timing solution replacing discrete PLL+fanout buffers, reducing board area by >40% and eliminating inter-stage jitter accumulation.	Use Scenario: Providing ITU-T G.8262-compliant EEC Option 1/2 clocks (e.g., 125 MHz, 156.25 MHz, 312.5 MHz) to multiple switch ASICs and PHYs in a 100G line card with redundant input sources. IC Role / Device Role / Timing Role: Primary jitter-attenuated clock source with automatic hitless switchover between primary and backup line clocks and stable holdover during loss-of-signal events. Use Value: Guarantees <1.5 μs phase transient during input failover and <±0.1 ppm frequency drift in holdover-meeting G.8262 wander limits over 24-hour periods.
Broadcast Video Synchronization	Test & Measurement Reference
Use Scenario: Deriving SMPTE ST 2059-2 compliant 27 MHz, 74.25 MHz, and 148.5 MHz video clocks from a GPS-disciplined 10 MHz reference in IP-based broadcast encoders. IC Role / Device Role / Timing Role: Low-jitter clock multiplier with DCO fine-tuning for genlock accuracy and zero-delay mode for minimal latency between reference and output. Use Value: Achieves <±1 ns video sample alignment across multiple outputs, eliminating frame sync errors in multi-camera production systems.	Use Scenario: Serving as programmable ultra-low-jitter reference in high-end oscilloscopes and bit error rate testers requiring multiple synchronized sampling clocks (e.g., 1 GHz, 500 MHz, 125 MHz) from one master source. IC Role / Device Role / Timing Role: Precision jitter attenuator with programmable loop bandwidth to suppress source oscillator phase noise while preserving signal integrity. Use Value: Delivers 90 fs rms jitter floor independent of input quality-enabling accurate jitter decomposition and margin testing at 10+ Gb/s data rates.

OTN Muxponder Timing

SyncE Carrier Ethernet Switch

Use Scenario: Generating synchronized 10.709 GHz, 12.890625 GHz, and 25.78125 GHz SerDes references from a single recovered 155.52 MHz or 622.08 MHz line clock in metro OTN muxponders.

IC Role / Device Role / Timing Role: Jitter attenuator and multi-frequency clock multiplier ensuring sub-100 fs rms jitter at all SerDes lanes to meet OTU-4 BER requirements.

Use Value: Enables single-chip timing solution replacing discrete PLL+fanout buffers, reducing board area by >40% and eliminating inter-stage jitter accumulation.

Use Scenario: Providing ITU-T G.8262-compliant EEC Option 1/2 clocks (e.g., 125 MHz, 156.25 MHz, 312.5 MHz) to multiple switch ASICs and PHYs in a 100G line card with redundant input sources.

IC Role / Device Role / Timing Role: Primary jitter-attenuated clock source with automatic hitless switchover between primary and backup line clocks and stable holdover during loss-of-signal events.

Use Value: Guarantees <1.5 μs phase transient during input failover and <±0.1 ppm frequency drift in holdover-meeting G.8262 wander limits over 24-hour periods.

Broadcast Video Synchronization

Test & Measurement Reference

Use Scenario: Deriving SMPTE ST 2059-2 compliant 27 MHz, 74.25 MHz, and 148.5 MHz video clocks from a GPS-disciplined 10 MHz reference in IP-based broadcast encoders.

IC Role / Device Role / Timing Role: Low-jitter clock multiplier with DCO fine-tuning for genlock accuracy and zero-delay mode for minimal latency between reference and output.

Use Value: Achieves <±1 ns video sample alignment across multiple outputs, eliminating frame sync errors in multi-camera production systems.

Use Scenario: Serving as programmable ultra-low-jitter reference in high-end oscilloscopes and bit error rate testers requiring multiple synchronized sampling clocks (e.g., 1 GHz, 500 MHz, 125 MHz) from one master source.

IC Role / Device Role / Timing Role: Precision jitter attenuator with programmable loop bandwidth to suppress source oscillator phase noise while preserving signal integrity.

Use Value: Delivers 90 fs rms jitter floor independent of input quality-enabling accurate jitter decomposition and margin testing at 10+ Gb/s data rates.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5345B-D-GM	Same 64-QFN package and DSPLL architecture but limited to 0.001–350 MHz output range and no fractional synthesis support.	Suitable for lower-frequency SyncE and enterprise switching where >350 MHz outputs are unnecessary.	Select only if application requires ≤350 MHz outputs and cost-sensitive design excludes fractional-N capability.
LTC6957-3	Analog Devices' 3-output jitter cleaner with 225 fs rms jitter, fixed 1.2 GHz max output, and no NVM or multi-synthesis flexibility.	Targeted at compact RF/data converter timing where ultra-low jitter is needed on ≤3 outputs and field reprogramming is not required.	Choose when board space is constrained, only 3 outputs are needed, and jitter budget allows 2.5× higher than SI5345A-B05765-GM.

Compared with Si5345B-D-GM, SI5345A-B05765-GM provides full 1028 MHz output capability and fractional synthesis for arbitrary frequency generation; compared with LTC6957-3, it offers 10x more outputs, integrated NVM, and superior 90 fs jitter-making it optimal for multi-protocol, high-density telecom timing.

Availability

SI5345A-B05765-GM is available at Aetrix Electronics and suitable for OTN transponders, SyncE carrier switches, broadcast video infrastructure, and test equipment requiring stable component supply, long-term lifecycle assurance, and factory-trimmed jitter performance.

Supply support for SI5345A-B05765-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5345 family is engineered as a high-channel-count, any-frequency jitter attenuator platform targeting next-generation telecom infrastructure where deterministic phase alignment, holdover resilience, and multi-standard clock synthesis are mandatory.

FAQ

What is the factory-programmed configuration of SI5345A-B05765-GM?

The SI5345A-B05765-GM is a custom factory preprogrammed variant of the Si5345A-D-GM1 device. Its unique "B05765" suffix indicates a specific ClockBuilder Pro-generated configuration stored in on-chip OTP NVM, guaranteeing defined output frequencies, input priorities, jitter bandwidth, and operational modes at power-up without host intervention.

Does SI5345A-B05765-GM support both I²C and SPI interfaces?

Yes, SI5345A-B05765-GM supports both I²C (SCL/SDA) and SPI (SCLK/SDIO/CSb) serial interfaces for configuration and monitoring. Interface selection is determined by strap pin states at power-up; I²C is default. Both interfaces allow full register access, status flag reads, and NVM programming-enabling in-system reconfiguration of SI5345A-B05765-GM without hardware changes.

How does SI5345A-B05765-GM achieve 90 fs rms jitter performance?

SI5345A-B05765-GM achieves 90 fs rms jitter through fourth-generation DSPLL architecture with fully integrated loop filter, optimized VCO design, and low-noise MultiSynth fractional-N synthesis. Its jitter specification is measured under standard conditions (125 MHz output, 12 kHz–20 MHz integration band) with 54 MHz crystal reference and proper PCB layout per Skyworks' reference design-ensuring repeatable performance in production systems.

Can SI5345A-B05765-GM operate without an external crystal?

No, SI5345A-B05765-GM requires an external crystal (25–54 MHz) connected to XA/XB pins for freerun and holdover mode stability. While it accepts external REFCLK on XA/XB, the crystal configuration is mandatory for achieving specified 90 fs jitter and meeting ITU-T G.8262 holdover requirements. Omitting the crystal degrades holdover accuracy and increases long-term frequency drift beyond spec.

What is the function of the IN3 pin on SI5345A-B05765-GM in zero-delay mode?

In zero-delay mode, the IN3 pin on SI5345A-B05765-GM is repurposed as FB_IN (feedback input) and is not available as a selectable clock input. This mode configures the DSPLL to lock the output phase to the IN3 signal, minimizing propagation delay between input and output-critical for applications like clock forwarding in FPGA-based timing bridges where deterministic latency is essential.

SI5345A-B05765-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

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Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

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SI5345A-B05765-GM FAQ

1.How can I place an order for SI5345A-B05765-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5345A-B05765-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5345A-B05765-GM reliable?

The price and inventory of SI5345A-B05765-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5345A-B05765-GM is usually 5 days.

3.What payment methods are accepted for SI5345A-B05765-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5345A-B05765-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5345A-B05765-GM?

SI5345A-B05765-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5345A-B05765-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5345A-B05765-GM?

For technical support, including SI5345A-B05765-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5345A-B05765-GM requirements.

6.How does Aetrix verify that SI5345A-B05765-GM is sourced from the original manufacturer or authorized distributors?

All SI5345A-B05765-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5345A-B05765-GM meets industry standards.

7.What is the process for return or replacement of SI5345A-B05765-GM?

All SI5345A-B05765-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5345A-B05765-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5345A-B05765-GM part is unused and in its original packaging.

Return procedure for SI5345A-B05765-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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