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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5345A-B05766-GM

Name: SI5345A-B05766-GM
Brand: Skyworks Solutions Inc.
SKU: SI5345A-B05766-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5345A-B05766-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5345A-B05766-GM.pdf

Description:: IC CLK MULTIPLIER ATTENUATOR

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Product details

Overview

SI5345A-B05766-GM from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier featuring fourth-generation DSPLL™ and MultiSynth™ technologies. It delivers ultra-low 90 fs rms jitter, supports 4 differential or LVCMOS inputs and 10 programmable outputs (LVDS/LVPECL/LVCMOS/CML/HCSL), and operates across –40 to +85 °C. It is used in OTN transponders and SyncE-compliant carrier Ethernet switches.

For engineers reviewing the SI5345A-B05766-GM datasheet, SI5345A-B05766-GM pinout, SI5345A-B05766-GM application, or SI5345A-B05766-GM equivalent, key selection considerations include jitter attenuation bandwidth (0.1 Hz–4 kHz), G.8262 EEC Option 1/2 compliance, hitless input switching, DCO mode with 0.001 ppb step size, and factory-programmable NVM configuration for known-power-up state.

Technical Context

The SI5345A-B05766-GM implements a digitally controlled DSPLL architecture with fully integrated loop filter and programmable loop bandwidth (0.1 Hz–4 kHz), enabling precise jitter filtering without external components. Its MultiSynth output dividers support both integer and fractional synthesis, allowing any-output-frequency generation from any-input-frequency.

It features automatic/manual input clock switching with hitless, ramped, and glitchless modes; status monitoring (LOS/OOF/LOL); and dual-mode operation-locked to input clocks or free-run/holdover using an internal oscillator driven by a 25–54 MHz crystal. The device uses in-circuit programmable OTP memory and supports I²C/SPI configuration via ClockBuilder Pro™.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (rms)	90 fs - meets stringent SyncE EEC Option 1/2 requirements for telecom timing integrity
Input range (diff)	8 kHz–750 MHz - supports legacy SONET/SDH and modern high-speed serial protocols
Output range (diff)	100 Hz–1028 MHz - covers Ethernet (1G/10G/100G), PCIe, and SerDes reference clocks
Jitter BW control	0.1 Hz–4 kHz digital programming - enables application-specific noise rejection tuning
Supply voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5% - ensures stable core/analog domain operation
Crystal frequency	25–54 MHz - allows use of low-cost, industry-standard crystals; 48–54 MHz recommended for best jitter
Temp range	–40 to +85 °C - qualified for industrial and telecom infrastructure environments
G.8262 compliance	EEC Option 1 & 2 - certifies suitability for Synchronous Ethernet line cards and muxponders

Pinout & Package

The SI5345A-B05766-GM is housed in a 64-QFN package (9 × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Skyworks Si5345 Rev D datasheet Section 9 (Pin Descriptions).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential/LVCMOS clock inputs	Four selectable reference inputs; IN3 serves as FB_IN in zero-delay mode
OUT0–OUT9	Programmable clock outputs	10 independent outputs supporting LVDS/LVPECL/LVCMOS/CML/HCSL with amplitude control
XA/XB	Crytal oscillator terminals	Connects 25–54 MHz fundamental-mode crystal; internal load caps eliminate external components
SCL/SDA	I²C interface	Two-wire serial control; compatible with standard I²C bus timing and voltage levels
SCLK/MOSI/MISO/CSB	SPI interface	4-wire SPI option with chip select; supports up to 50 MHz clock rate
INTRb	Interrupt output	Open-drain status flag for LOS/OOF/LOL events; simplifies fault monitoring in system firmware
RSTb	Hardware reset	Active-low asynchronous reset; triggers full initialization and NVM reload
VDD/VDDA	Power supplies	VDD (1.8 V) powers digital logic; VDDA (3.3 V) powers analog/PLL circuits - requires separate filtering

Key Features

Feature	Design Value
Any-frequency synthesis	Generates arbitrary output frequencies from any input frequency using fractional P/N/R dividers
Hitless input switching	Eliminates phase transients when switching between fractionally related clocks (e.g., 156.25 MHz ↔ 312.5 MHz)
DCO mode	Enables fine frequency tuning with 0.001 ppb resolution via FINC/FDEC pins or register writes
Holdover with history	Stores 120 s of locked-frequency history; calculates averaged holdover frequency from programmable window
Zero-delay mode	Configures IN3 as feedback input to align OUTx phase with IN0–IN2 - critical for deterministic latency paths
Status monitoring	Real-time detection of Loss of Signal (LOS), Out of Frequency (OOF), and Loss of Lock (LOL) on all inputs

Applications

OTN Muxponders	SyncE Carrier Switches
Use Scenario: Aggregating multiple client-side 10G/100G signals into a single OTU4 line-side interface with strict jitter accumulation limits. IC Role / Device Role / Timing Role: Jitter attenuator and multi-rate clock multiplier providing clean, synchronized references for SERDES, FEC, and framing logic. Use Value: 90 fs rms jitter ensures compliance with ITU-T G.709 and G.8251 mask requirements at line rates up to 112 Gbps.	Use Scenario: Providing traceable, stratum-3E-compliant clocks across distributed switch fabric and packet processing units in a 100G Ethernet aggregation platform. IC Role / Device Role / Timing Role: Primary timing engine delivering G.8262 EEC Option 2–compliant outputs to PHYs, MACs, and traffic managers. Use Value: Programmable jitter attenuation bandwidth (0.1 Hz) enables optimal wander suppression while maintaining fast lock acquisition during network reconfiguration.
Broadcast Video Systems	Test & Measurement Equipment
Use Scenario: Generating genlock-capable pixel clocks (e.g., 74.25 MHz, 148.5 MHz) and audio word clocks (48 kHz, 96 kHz) from a common SMPTE 2059 PTP grandmaster. IC Role / Device Role / Timing Role: Multi-format clock synthesizer with sub-picosecond phase alignment across video/audio domains. Use Value: Independent output supply pins (1.8/2.5/3.3 V) and programmable common-mode voltage enable direct interfacing with diverse video DACs, ADCs, and FPGA I/O banks.	Use Scenario: Serving as the master clock source in high-resolution oscilloscopes and bit-error-rate testers requiring ultra-low phase noise and flexible frequency agility. IC Role / Device Role / Timing Role: Low-jitter, software-reconfigurable timing reference with DCO mode for swept-frequency jitter tolerance testing. Use Value: 0.001 ppb DCO step size and glitchless on-the-fly frequency changes allow precise stimulus control without hardware reconfiguration.

OTN Muxponders

SyncE Carrier Switches

Use Scenario: Aggregating multiple client-side 10G/100G signals into a single OTU4 line-side interface with strict jitter accumulation limits.

IC Role / Device Role / Timing Role: Jitter attenuator and multi-rate clock multiplier providing clean, synchronized references for SERDES, FEC, and framing logic.

Use Value: 90 fs rms jitter ensures compliance with ITU-T G.709 and G.8251 mask requirements at line rates up to 112 Gbps.

Use Scenario: Providing traceable, stratum-3E-compliant clocks across distributed switch fabric and packet processing units in a 100G Ethernet aggregation platform.

IC Role / Device Role / Timing Role: Primary timing engine delivering G.8262 EEC Option 2–compliant outputs to PHYs, MACs, and traffic managers.

Use Value: Programmable jitter attenuation bandwidth (0.1 Hz) enables optimal wander suppression while maintaining fast lock acquisition during network reconfiguration.

Broadcast Video Systems

Test & Measurement Equipment

Use Scenario: Generating genlock-capable pixel clocks (e.g., 74.25 MHz, 148.5 MHz) and audio word clocks (48 kHz, 96 kHz) from a common SMPTE 2059 PTP grandmaster.

IC Role / Device Role / Timing Role: Multi-format clock synthesizer with sub-picosecond phase alignment across video/audio domains.

Use Value: Independent output supply pins (1.8/2.5/3.3 V) and programmable common-mode voltage enable direct interfacing with diverse video DACs, ADCs, and FPGA I/O banks.

Use Scenario: Serving as the master clock source in high-resolution oscilloscopes and bit-error-rate testers requiring ultra-low phase noise and flexible frequency agility.

IC Role / Device Role / Timing Role: Low-jitter, software-reconfigurable timing reference with DCO mode for swept-frequency jitter tolerance testing.

Use Value: 0.001 ppb DCO step size and glitchless on-the-fly frequency changes allow precise stimulus control without hardware reconfiguration.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5345B-D-GM	Same 64-QFN package and pinout; limited to 350 MHz max output frequency (vs. 1028 MHz)	Suitable for sub-10G applications only; not compliant with 100G Ethernet or OTU4 line rates	Select only if output frequency ≤350 MHz and cost sensitivity outweighs future scalability needs
LMK04832ISQE/NOPB	2× PLL architecture; higher power consumption (1.2 W vs. ~0.7 W); no integrated crystal oscillator	Requires external TCXO/OCXO for holdover; better suited for RF sampling and radar where dual-loop flexibility is critical	Choose when needing cascaded jitter cleaning or deterministic delay calibration not supported by Si5345's single-DSPLL architecture

Compared with SI5345A-B05766-GM, Si5345B-D-GM sacrifices high-frequency capability for lower cost, while LMK04832ISQE/NOPB trades integration and jitter performance for architectural flexibility in mixed-signal test systems.

Availability

SI5345A-B05766-GM is available at Aetrix Electronics and suitable for OTN transponders, Synchronous Ethernet switches, and broadcast video equipment requiring stable component supply, long-term lifecycle assurance, and guaranteed factory-programmed configurations.

Supply support for SI5345A-B05766-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications, automotive, and industrial markets.

The Si5345 family is designed specifically for high-performance timing in telecom infrastructure, delivering jitter-attenuated, multi-output clocks with G.8262 compliance and field-programmable flexibility - targeting OTN, SyncE, and broadcast video systems.

FAQ

What is the primary function of the SI5345A-B05766-GM in a telecom timing architecture?

The SI5345A-B05766-GM serves as a jitter-attenuating clock multiplier that cleans and regenerates timing signals from noisy or unstable sources. It locks to one of four input clocks (e.g., from a SyncE line card or PTP grandmaster), suppresses incoming jitter using its digitally programmable DSPLL loop bandwidth, and generates up to ten low-jitter outputs for downstream SERDES, PHYs, and processors. Its 90 fs rms jitter and G.8262 EEC Option 1/2 compliance make it suitable for stratum-3E timing distribution in OTN and carrier Ethernet systems. SI5345A-B05766-GM achieves this with integrated crystal oscillator support and factory-programmed NVM configuration.

Does the SI5345A-B05766-GM support both I²C and SPI interfaces for configuration?

Yes, the SI5345A-B05766-GM supports both I²C (SCL/SDA) and SPI (SCLK/MOSI/MISO/CSB) serial interfaces for register configuration and status readback. Interface selection is determined by strap pin settings at power-up. Both interfaces operate with standard voltage levels (1.8 V or 3.3 V I/O) and support in-circuit programming of its non-volatile memory. ClockBuilder Pro™ software abstracts low-level register access for both protocols, enabling rapid frequency plan development and validation. SI5345A-B05766-GM retains its last programmed configuration in OTP memory and powers up ready to operate without host intervention.

How does the holdover functionality of the SI5345A-B05766-GM maintain timing accuracy during input clock loss?

When all valid input clocks fail, the SI5345A-B05766-GM enters holdover mode and uses an averaged historical frequency value derived from up to 120 seconds of prior locked operation. This average is calculated over a user-programmable time window to exclude corrupted data near the failure point. The DSPLL then pulls its output frequency to this averaged value using the crystal reference (25–54 MHz) on XA/XB. Holdover stability depends entirely on crystal accuracy and aging - a TCXO is recommended for SyncE pizza-box applications requiring <0.1 ppm drift. SI5345A-B05766-GM exits holdover glitchlessly upon input restoration, optionally ramping output frequency to minimize transient impact.

Can the SI5345A-B05766-GM generate different output formats simultaneously?

Yes, the SI5345A-B05766-GM supports simultaneous output of LVDS, LVPECL, LVCMOS, CML, and HCSL signal formats across its 10 outputs. Each output has independent format selection, programmable amplitude, common-mode voltage (for differential outputs), and drive strength. For example, OUT0 can be configured as 3.3 V LVCMOS for an FPGA clock input, while OUT5 runs as 2.5 V LVDS for a 10G Ethernet PHY, and OUT9 operates as HCSL for a PCIe Gen4 root complex - all from the same SI5345A-B05766-GM device. This eliminates need for external level translators and reduces board space and BOM count.

Is the SI5345A-B05766-GM pin-compatible with other devices in the Si5345 family?

Yes, all Si5345 variants - including SI5345A-B05766-GM, SI5345B-D-GM, and SI5345C-D-GM - share identical 64-QFN (9×9 mm) packaging and pinout. Differences lie solely in factory-programmed frequency limits and synthesis modes (e.g., integer-only vs. fractional), not electrical or mechanical compatibility. This allows drop-in replacement during design iteration or volume production without PCB layout changes. SI5345A-B05766-GM is preprogrammed for full 0.001–1028 MHz output range with integer+fractional synthesis, distinguishing it functionally but not physically from other Si5345 members.

SI5345A-B05766-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

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Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

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SI5345A-B05766-GM FAQ

1.How can I place an order for SI5345A-B05766-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5345A-B05766-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5345A-B05766-GM reliable?

The price and inventory of SI5345A-B05766-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5345A-B05766-GM is usually 5 days.

3.What payment methods are accepted for SI5345A-B05766-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5345A-B05766-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5345A-B05766-GM?

SI5345A-B05766-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5345A-B05766-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5345A-B05766-GM?

For technical support, including SI5345A-B05766-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5345A-B05766-GM requirements.

6.How does Aetrix verify that SI5345A-B05766-GM is sourced from the original manufacturer or authorized distributors?

All SI5345A-B05766-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5345A-B05766-GM meets industry standards.

7.What is the process for return or replacement of SI5345A-B05766-GM?

All SI5345A-B05766-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5345A-B05766-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5345A-B05766-GM part is unused and in its original packaging.

Return procedure for SI5345A-B05766-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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