Skyworks Solutions Inc. SI5345A-B05771-GM
- Part No.:
- SI5345A-B05771-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- -
- Datasheet:
-
SI5345A-B05771-GM.pdf
- Description:
- IC CLK MULTIPLIER ATTENUATOR
- Quantity:
- Payment:

- Shipping:

Inventory:1,264
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5345A-B05771-GM from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier IC featuring fourth-generation DSPLL™ and MultiSynth™ technologies. It delivers ultra-low 90 fs rms jitter, supports 4 differential or LVCMOS inputs and 10 programmable outputs (LVDS/LVPECL/LVCMOS/CML/HCSL), and operates across –40 to +85 °C. It powers up with factory-programmed configuration and serves as the primary clock synthesis and jitter cleaning engine in SyncE-compliant line cards.
For engineers reviewing the SI5345A-B05771-GM datasheet, SI5345A-B05771-GM pinout, SI5345A-B05771-GM application, or SI5345A-B05771-GM equivalent, key selection considerations include its G.8262 EEC Option 1/2 compliance, digitally programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), hitless/ramped/glitchless input switching, DCO mode with 0.001 ppb step size, and support for gapped clock locking - all critical for carrier-grade timing integrity.
Technical Context
The SI5345A-B05771-GM implements a fourth-generation DSPLL architecture with fractional input dividers (P), fractional MultiSynth output dividers (N), and integer output dividers (R), enabling any-frequency synthesis from any input. Its loop filter is fully integrated on-chip, eliminating external components and noise coupling risks.
It supports three operational modes - freerun (crystal-referenced), locked (input-synchronized), and holdover (averaged historical frequency storage up to 120 s) - with automatic/manual input selection, status monitoring (LOS/OOF/LOL), and I²C/SPI control of non-volatile OTP memory for deterministic power-up behavior.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Jitter (rms) | 90 fs - meets stringent ITU-T G.8262 EEC Option 1 & 2 requirements for Synchronous Ethernet. |
| Input range (diff) | 8 kHz–750 MHz - accepts OC-192/STM-64, 10G/100G Ethernet, and SONET/SDH reference clocks. |
| Output range (diff) | 100 Hz–1028 MHz - covers baseband, SerDes, and high-speed interface frequencies including PCIe Gen5 and DDR5. |
| Jitter BW | 0.1 Hz–4 kHz - digitally programmable to optimize attenuation vs. wander trade-off per application. |
| Supply voltages | VDD = 1.8 V ±5%, VDDA = 3.3 V ±5% - enables low-power core operation with robust analog supply for precision timing. |
| Temp range | –40 to +85 °C - qualified for industrial and telecom infrastructure environments without derating. |
| Crystal freq | 25–54 MHz - internal loading capacitors eliminate external caps; 48–54 MHz recommended for best jitter. |
Pinout & Package
SI5345A-B05771-GM uses a 64-pin QFN package (9 × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5345 64-QFN pinout specification, supporting four clock inputs (IN0–IN3), ten outputs (OUT0–OUT9), crystal interface (XA/XB), serial control (SDA/SCL/MOSI/MISO/SCLK/CSB), and dedicated status/enable pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN0–IN3 | Differential or LVCMOS clock inputs | Support automatic/manual selection; IN3 becomes FB_IN in zero-delay mode. |
| OUT0–OUT9 | Programmable clock outputs | Configurable for LVDS/LVPECL/LVCMOS/CML/HCSL with independent amplitude and common-mode control. |
| XA/XB | Crytal oscillator terminals | Internal 2×CL loading eliminates external caps; supports 25–54 MHz fundamental-mode crystals. |
| SCL/SDA or SCLK/MOSI/MISO/CSB | I²C or SPI serial interface | Enables in-circuit programming of OTP NVM; supports factory preconfiguration and field updates. |
| INTRb | Interrupt output | Asserts on LOS/OOF/LOL events; enables real-time fault monitoring without polling. |
Key Features
| Feature | Design Value |
|---|---|
| Hitless input switching | Eliminates phase transients when switching between fractionally related inputs (e.g., 155.52 MHz ↔ 622.08 MHz), preserving system timing alignment. |
| Ramped holdover exit | Linearly transitions output frequency using user-selectable ramp rates (0.2–40,000 ppm/s), preventing glitches during recovery from input failure. |
| Gapped clock lock | Locks to modulated or missing-cycle inputs (e.g., burst-mode SyncE), enabling robust timing in packet-based transport networks. |
| DCO mode | Provides fine frequency tuning (0.001 ppb step) via FINC/FDEC pins or register writes - essential for TDM slip compensation and frequency calibration. |
| Integrated loop filter | Removes external passive components, reducing PCB area, BOM count, and susceptibility to board-level noise coupling. |
Applications
| OTN Muxponder | SyncE Line Card |
|---|---|
Use Scenario: Aggregating multiple client-side OTN signals into a single DWDM line-side interface with strict jitter and wander limits. IC Role / Device Role / Timing Role: Jitter attenuator and multi-rate clock generator providing clean, synchronized clocks for OTU frame mapping, FEC, and multiplexing logic. Use Value: Meets ITU-T G.709 OPUk/ODUk jitter masks and G.8262 EEC Option 2 via 90 fs rms performance and programmable loop bandwidth. | Use Scenario: Carrier Ethernet transport node requiring traceable, stratum-3E-compliant timing across 10G/100G interfaces. IC Role / Device Role / Timing Role: Primary timing IC delivering G.8262-compliant outputs for PTP grandmaster synchronization and SERDES clocking. Use Value: Enables holdover stability <±0.1 ppm over 24 h using averaged historical frequency data and TCXO-referenced free-run mode. |
| Broadcast Video Router | Test & Measurement Instrument |
Use Scenario: Frame-accurate routing of SMPTE 2110/2022-6 video streams across IP infrastructure with genlock and lip-sync requirements. IC Role / Device Role / Timing Role: Multi-output clock synthesizer generating synchronous 74.25 MHz, 148.5 MHz, and 297 MHz pixel clocks from a single reference. Use Value: Supports glitchless on-the-fly frequency changes and zero-delay mode to maintain video pipeline continuity during source switching. | Use Scenario: High-precision signal analyzer requiring ultra-low-jitter sampling clocks for FFT-based spectral analysis up to 1 GHz. IC Role / Device Role / Timing Role: Jitter-cleaned master clock source feeding ADCs, DACs, and FPGA-based digital downconverters. Use Value: Delivers 90 fs rms jitter at 1 GHz output - 3× lower than typical PLL-based solutions - directly improving SFDR and ENOB. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar jitter attenuator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5345B-D-GM | Same 64-QFN package and DSPLL architecture but limited to 0.001–350 MHz output range and no fractional synthesis. | Suitable for sub-350 MHz applications (e.g., 10G Ethernet PHY, CPRI), not for 100G/400G SerDes or high-frequency RF sampling. | Select only if output frequency range and integer-only synthesis meet design requirements; SI5345A-B05771-GM offers full 1028 MHz coverage and fractional flexibility. |
| LTC6957-3 | 3-output jitter cleaner with 116 fs rms jitter, fixed 3.3 V supply, no NVM, and no holdover mode. | Targeted at instrumentation and low-channel-count systems; lacks multi-input auto-switching, gapped clock support, and SyncE compliance. | Choose for compact, low-power, 3-output designs where holdover, automatic redundancy, and EEC compliance are not required. |
Compared with SI5345B-D-GM and LTC6957-3, the SI5345A-B05771-GM uniquely combines 10 outputs, full 1028 MHz range, fractional synthesis, 120-second holdover history, and G.8262 EEC Option 1/2 certification - making it the only option for carrier-class multi-terabit line cards requiring deterministic timing recovery and multi-standard interoperability.
Availability
SI5345A-B05771-GM is available at Aetrix Electronics and suitable for OTN muxponders, Synchronous Ethernet line cards, and broadcast video infrastructure requiring stable component supply, long-term lifecycle assurance, and guaranteed traceable sourcing.
Supply support for SI5345A-B05771-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5345 family is engineered for carrier-grade timing applications, delivering ultra-low jitter, multi-input redundancy, and SyncE/ITU-T compliance in telecom, datacom, and broadcast infrastructure equipment.
FAQ
What is the primary function of the SI5345A-B05771-GM in a telecom timing architecture?
The SI5345A-B05771-GM serves as a jitter-attenuating clock multiplier that cleans and regenerates timing signals from noisy or unstable references. In telecom systems, it provides G.8262-compliant outputs for Synchronous Ethernet line cards, enabling precise synchronization across 10G/100G interfaces while supporting holdover during input failures. The SI5345A-B05771-GM achieves this using its integrated DSPLL and MultiSynth architecture with factory-programmed NVM configuration.
Does the SI5345A-B05771-GM support automatic input clock switching with priority-based selection?
Yes, the SI5345A-B05771-GM includes an automatic input selection state machine that evaluates input qualification (LOS/OOF), user-defined priority order, and revertive/non-revertive behavior. It seamlessly switches among IN0–IN3 based on validity and priority, entering holdover only when no valid inputs remain. This capability is integral to the SI5345A-B05771-GM's role in redundant timing architectures for carrier Ethernet and OTN equipment.
Can the SI5345A-B05771-GM generate output frequencies not harmonically related to its input?
Yes, the SI5345A-B05771-GM uses fractional-N synthesis in both its DSPLL and MultiSynth stages to generate any output frequency from any input frequency - including non-harmonic, irrational, or widely disparate ratios (e.g., 125 MHz input → 156.25 MHz output). This "any-frequency" capability is enabled by programmable P, N, and R dividers and is a defining feature of the SI5345A-B05771-GM across its full 100 Hz–1028 MHz output range.
How does the SI5345A-B05771-GM handle loss of input clock during operation?
Upon input failure, the SI5345A-B05771-GM automatically enters holdover mode, using up to 120 seconds of stored historical frequency data to compute an averaged holdover frequency. Its output remains phase-continuous and drifts only according to the stability of the XA/XB crystal or TCXO. The SI5345A-B05771-GM exits holdover glitchlessly when a valid input returns, optionally using ramped frequency transition to avoid transients - a key reliability feature for the SI5345A-B05771-GM in mission-critical infrastructure.
Is the SI5345A-B05771-GM preprogrammed, and how is configuration managed?
Yes, SI5345A-B05771-GM is a factory preprogrammed part (denoted by "B05771" in the OPN), meaning its NVM contains a specific frequency plan and operational settings assigned by Skyworks and generated via ClockBuilder Pro™. Configuration can be updated in-circuit via I²C or SPI, but the SI5345A-B05771-GM powers up immediately with its programmed state - eliminating boot-time uncertainty and simplifying system integration.
SI5345A-B05771-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- *
- Package/Case:
- -
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Divider/Multiplier:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- -
SI5345A-B05771-GM FAQ
1.How can I place an order for SI5345A-B05771-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5345A-B05771-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5345A-B05771-GM reliable?
The price and inventory of SI5345A-B05771-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5345A-B05771-GM is usually 5 days.
3.What payment methods are accepted for SI5345A-B05771-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5345A-B05771-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5345A-B05771-GM?
SI5345A-B05771-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5345A-B05771-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5345A-B05771-GM?
For technical support, including SI5345A-B05771-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5345A-B05771-GM requirements.
6.How does Aetrix verify that SI5345A-B05771-GM is sourced from the original manufacturer or authorized distributors?
All SI5345A-B05771-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5345A-B05771-GM meets industry standards.
7.What is the process for return or replacement of SI5345A-B05771-GM?
All SI5345A-B05771-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5345A-B05771-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5345A-B05771-GM part is unused and in its original packaging.
Return procedure for SI5345A-B05771-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5345A-B05771-GM Tags
-
CD74HCT4046AM96
Texas Instruments

-
MC14046BDWR2G
onsemi

-
501MILFT
Renesas
-
CD74HC7046AM
Texas Instruments
-
CDCVF2505PWR
Texas Instruments

-
RC19004A100GNL#KB0
Renesas
-
SI5351A-B-GTR
Skyworks Solutions Inc.

-
CY2305SXI-1T
Infineon Technologies

-
570BILFT
Renesas

-
CDCE913PWR
Texas Instruments

-
CY2305SXI-1HT
Infineon Technologies

-
DS1086LU+T
Analog Devices Inc./Maxim Integrated
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
