Skyworks Solutions Inc. SI5345A-B05975-GM

Overview

SI5345A-B05975-GM from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier featuring fourth-generation DSPLL™ and MultiSynth™ technologies. It delivers ultra-low 90 fs rms jitter, supports differential inputs up to 750 MHz and outputs up to 1028 MHz, and operates in free-run, synchronous, or holdover modes - enabling precise clock synthesis for SyncE-compliant 100 GbE line cards.

For engineers reviewing the SI5345A-B05975-GM datasheet, SI5345A-B05975-GM pinout, SI5345A-B05975-GM application, or SI5345A-B05975-GM equivalent, key selection considerations include its programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), G.8262 EEC Option 1/2 compliance, 64-QFN 9×9 mm package, I²C/SPI configurability, and factory preprogrammed NVM configuration.

Technical Context

The SI5345A-B05975-GM implements a digitally controlled DSPLL with fully integrated loop filter and programmable loop bandwidth (0.1 Hz–4 kHz), enabling application-level jitter optimization. Its MultiSynth architecture supports fractional-N synthesis across all 10 outputs, with independent R-divider synchronization and crosspoint routing between any MultiSynth and output.

It features hitless input switching for fractionally related clocks, ramped switching for plesiochronous sources, and DCO mode with 0.001 ppb step resolution. Input qualification includes LOS/OOF detection, while output drivers support LVDS, LVPECL, LVCMOS, CML, and HCSL with programmable amplitude and common-mode voltage.

Key Specifications

Pinout & Package

The SI5345A-B05975-GM is housed in a 64-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5345 Rev D datasheet Section 9 (Pin Descriptions).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator/clock multiplier applications.

Compared with SI5345A-B05975-GM, Si5345B-D-GM reduces frequency range and synthesis flexibility but lowers BOM cost, while LTC6957-3 trades channel count and programmability for lower power and smaller footprint - making SI5345A-B05975-GM optimal for high-density, multi-protocol telecom timing systems requiring field-upgradable configurations.

Availability

SI5345A-B05975-GM is available at Aetrix Electronics and suitable for OTN muxponders, SyncE line cards, and broadcast video routers requiring stable component supply, long-term lifecycle assurance, and factory-trimmed jitter performance.

Supply support for SI5345A-B05975-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications infrastructure, automotive, and industrial markets.

The SI5345A-B05975-GM belongs to Skyworks' Si5345 family of jitter-attenuating clock multipliers, designed specifically for high-reliability, multi-protocol timing in 100G+ networking and broadcast systems where G.8262 compliance and field-programmable flexibility are mandatory.

FAQ

What is the primary function of the SI5345A-B05975-GM in a telecom timing system?

The SI5345A-B05975-GM serves as a jitter-attenuating clock multiplier that cleans and regenerates high-frequency reference clocks for 100GbE, OTN, and SyncE applications. It accepts noisy or gapped input clocks, applies digital PLL-based filtering, and generates up to 10 ultra-low-jitter (90 fs rms) outputs - ensuring compliance with ITU-T G.8262 EEC Option 1/2. The SI5345A-B05975-GM achieves this using fourth-generation DSPLL™ and MultiSynth™ technology with integrated loop filter and programmable bandwidth.

Does the SI5345A-B05975-GM require an external crystal, and what frequency range is supported?

Yes, the SI5345A-B05975-GM requires an external crystal connected to XA/XB pins for stable free-run and holdover operation. It supports crystals from 25 MHz to 54 MHz, with Skyworks recommending 48–54 MHz for optimal jitter performance. Internal loading capacitors eliminate the need for external CL components. The SI5345A-B05975-GM also supports external REFCLK inputs up to 54 MHz via PREF divider, but crystal operation is preferred for lowest phase noise.

How does the SI5345A-B05975-GM handle input clock failures in a redundant timing architecture?

The SI5345A-B05975-GM automatically enters holdover mode upon input failure, using up to 120 seconds of stored frequency history to compute an averaged holdover frequency. This minimizes phase disturbance during switchover. The holdover window size and delay are programmable, and exit from holdover can be ramped to avoid glitches. The SI5345A-B05975-GM maintains frequency accuracy dependent on the XA/XB crystal - achieving <±0.01 ppm drift over 24 hours with a TCXO.

Can the SI5345A-B05975-GM generate different output formats simultaneously, and which ones are supported?

Yes, the SI5345A-B05975-GM supports simultaneous output of LVDS, LVPECL, LVCMOS, CML, and HCSL signal formats across its 10 outputs. Each output is independently configurable for format, amplitude, common-mode voltage (for differential), and impedance (for LVCMOS). This allows direct interfacing with diverse SERDES, FPGA, ASIC, and PHY devices without level-shifting components - a key capability enabled by the SI5345A-B05975-GM's per-output driver architecture.

Is the SI5345A-B05975-GM preprogrammed, and how is configuration performed?

Yes, the SI5345A-B05975-GM is a factory preprogrammed variant (denoted by "B05975" in the part number), meaning its NVM contains a specific frequency plan and operational settings assigned by Skyworks. Configuration is performed via I²C or SPI interface using ClockBuilder Pro™ software; the SI5345A-B05975-GM powers up immediately with its stored configuration and requires no host initialization. Field updates remain possible through in-circuit programming of the OTP memory.