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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5345A-B06103-GMR

Name: SI5345A-B06103-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5345A-B06103-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5345A-B06103-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5345A-B06103-GMR.pdf

Description:: IC CLK MULTIPLIER ATTENUATOR

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Product details

Overview

SI5345A-B06103-GMR from Skyworks is a 10-channel, any-frequency jitter attenuator and clock multiplier IC featuring fourth-generation DSPLL™ and MultiSynth™ technology. It delivers ultra-low 90 fs rms jitter, supports differential inputs up to 750 MHz and outputs up to 1028 MHz, and operates in free-run, locked, or holdover modes - enabling precise timing for OTN transponders and SyncE-compliant carrier Ethernet switches.

For engineers reviewing the SI5345A-B06103-GMR datasheet, SI5345A-B06103-GMR pinout, SI5345A-B06103-GMR application, or SI5345A-B06103-GMR equivalent, key selection considerations include its programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), G.8262 EEC Option 1/2 compliance, I²C/SPI configurability with on-chip NVM, and support for LVDS/LVPECL/LVCMOS/CML/HCSL output formats with independent supply pins.

Technical Context

The SI5345A-B06103-GMR implements a digitally controlled DSPLL architecture with fractional input dividers (P), multi-stage MultiSynth frequency synthesis (N), and integer output division (R), enabling hitless switching between fractionally related inputs and glitchless on-the-fly output frequency changes. Its integrated loop filter eliminates external passive components and noise coupling risks.

It features fully programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), Fastlock mode for accelerated lock acquisition, DCO mode with 0.001 ppb step resolution, and synchronized ramped holdover exit using user-defined ramp rates (0.2–40,000 ppm/s). Status monitoring includes LOS, OOF, and LOL flags with interrupt pin (INTRb) support.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (rms)	90 fs - meets stringent ITU-T G.8262 EEC Option 1/2 requirements for SyncE line cards.
Input range (diff)	8 kHz–750 MHz - accepts common telecom and datacom reference clocks including SONET/SDH and Ethernet rates.
Output range (diff)	100 Hz–1028 MHz - covers OC-192, 10G/100G Ethernet, and broadcast video pixel clocks.
Jitter BW control	0.1 Hz–4 kHz digital setting - enables application-level optimization of jitter filtering vs. transient response.
Supply voltages	VDD = 1.8 V ±5%; VDDA = 3.3 V ±5%; independent output supplies (1.8/2.5/3.3 V) - supports mixed-signal board integration.
Crystal reference	25–54 MHz XTAL - internal load caps eliminate external capacitors; 48–54 MHz recommended for best jitter performance.
Operating temp	–40 °C to +85 °C - qualified for industrial and telecom infrastructure environments.
Compliance	ITU-T G.8262 EEC Option 1 & 2 - certified for Synchronous Ethernet timing applications.

Pinout & Package

SI5345A-B06103-GMR is housed in a 64-pin QFN package (9 × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5345 pinout documentation (Rev D, Section 9).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential/single-ended clock inputs	Four configurable inputs supporting automatic/manual switching, gapped clock lock, and hitless transition between fractionally related sources.
OUT0–OUT9	Programmable clock outputs	10 independently configurable outputs with format (LVDS/LVPECL/etc.), amplitude, common-mode voltage, and enable control.
XA/XB	Crytal oscillator terminals	Connects 25–54 MHz crystal; internal load caps eliminate external components and reduce noise sensitivity.
SCL/SDA	I²C serial interface	Two-wire bus for configuration, status readback, and NVM programming without requiring SPI hardware.
INTRb	Interrupt output	Active-low open-drain flag indicating LOS, OOF, or LOL events - enables real-time fault monitoring in carrier systems.
RSTb	Hardware reset	Asynchronous active-low pin triggering full initialization and NVM register reload - ensures deterministic power-up state.

Key Features

Feature	Design Value
Any-frequency synthesis	Generates arbitrary output frequencies from any input via fractional P/N/R dividers - eliminates need for multiple fixed-ratio clock ICs.
Hitless input switching	Preserves output phase continuity when switching between fractionally related inputs - critical for zero-downtime network synchronization.
Programmable holdover	Uses 120-second frequency history window to compute stable holdover frequency - minimizes phase disturbance during input failure in SyncE systems.
DCO mode	0.001 ppb frequency step resolution via FINC/FDEC pins or register - enables fine-grained timing calibration in test & measurement equipment.
Zero delay mode	Configurable IN3 as FB_IN for phase-aligned feedback path - supports low-latency clock distribution in FPGA-based timing systems.
Status monitoring	Real-time LOS/OOF/LOL detection with interrupt assertion - simplifies system-level fault isolation in OTN muxponders and line cards.

Applications

OTN Muxponders	SyncE Carrier Switches
Use Scenario: Aggregating multiple client-side 10G/100G Ethernet streams into a single OTN line-side interface with strict jitter and wander limits. IC Role / Device Role / Timing Role: Jitter attenuator and multi-rate clock multiplier providing clean, synchronized clocks to OTN framers and FEC engines. Use Value: Meets ITU-T G.709 jitter transfer and generation masks while enabling flexible rate adaptation across heterogeneous client interfaces.	Use Scenario: Providing primary and backup timing references in carrier-grade Ethernet switches compliant with ITU-T G.8262. IC Role / Device Role / Timing Role: Synchronous Ethernet Equipment Clock (EEC) generating Stratum 3E-compliant outputs with holdover stability. Use Value: Achieves <±4.6 ppm frequency accuracy in holdover using averaged historical lock data - exceeds G.8262 EEC Option 2 requirements.
Broadcast Video Systems	Test & Measurement Instruments
Use Scenario: Distributing pixel-accurate timing across HD/4K/8K video processing pipelines with minimal skew and jitter-induced artifacts. IC Role / Device Role / Timing Role: Multi-output clock generator delivering synchronized LVDS clocks to image sensors, ADCs, and video encoders. Use Value: 90 fs rms jitter ensures sub-pixel timing integrity; programmable output formats match diverse video IC interface requirements.	Use Scenario: Calibrating high-resolution signal analyzers and arbitrary waveform generators requiring ultra-stable, tunable reference clocks. IC Role / Device Role / Timing Role: Digitally controlled oscillator (DCO) and jitter-cleaned reference source with fine frequency resolution. Use Value: 0.001 ppb DCO step size enables traceable frequency sweeps; programmable jitter BW optimizes phase noise for specific measurement bandwidths.

OTN Muxponders

SyncE Carrier Switches

Use Scenario: Aggregating multiple client-side 10G/100G Ethernet streams into a single OTN line-side interface with strict jitter and wander limits.

IC Role / Device Role / Timing Role: Jitter attenuator and multi-rate clock multiplier providing clean, synchronized clocks to OTN framers and FEC engines.

Use Value: Meets ITU-T G.709 jitter transfer and generation masks while enabling flexible rate adaptation across heterogeneous client interfaces.

Use Scenario: Providing primary and backup timing references in carrier-grade Ethernet switches compliant with ITU-T G.8262.

IC Role / Device Role / Timing Role: Synchronous Ethernet Equipment Clock (EEC) generating Stratum 3E-compliant outputs with holdover stability.

Use Value: Achieves <±4.6 ppm frequency accuracy in holdover using averaged historical lock data - exceeds G.8262 EEC Option 2 requirements.

Broadcast Video Systems

Test & Measurement Instruments

Use Scenario: Distributing pixel-accurate timing across HD/4K/8K video processing pipelines with minimal skew and jitter-induced artifacts.

IC Role / Device Role / Timing Role: Multi-output clock generator delivering synchronized LVDS clocks to image sensors, ADCs, and video encoders.

Use Value: 90 fs rms jitter ensures sub-pixel timing integrity; programmable output formats match diverse video IC interface requirements.

Use Scenario: Calibrating high-resolution signal analyzers and arbitrary waveform generators requiring ultra-stable, tunable reference clocks.

IC Role / Device Role / Timing Role: Digitally controlled oscillator (DCO) and jitter-cleaned reference source with fine frequency resolution.

Use Value: 0.001 ppb DCO step size enables traceable frequency sweeps; programmable jitter BW optimizes phase noise for specific measurement bandwidths.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5345A-D-GM1	Same silicon, factory-programmed with default configuration; no OTP NVM preloaded with custom frequency plan.	Requires post-manufacture configuration via ClockBuilder Pro; lacks pre-verified SyncE timing profile.	Select when design flexibility and field reprogramming are prioritized over time-to-market for production units.
LTC6955IUKG-1#PBF	5-output jitter cleaner (vs. 10); 115 fs rms jitter; supports only integer synthesis; no holdover or DCO mode.	Limited channel count and feature set - suitable for simpler timing trees but not OTN or multi-protocol SyncE line cards.	Choose only for cost-sensitive, lower-channel-count applications where G.8262 compliance is not required.

Compared with SI5345A-B06103-GMR, Si5345A-D-GM1 offers identical hardware capability but requires configuration after soldering, whereas LTC6955IUKG-1#PBF provides fewer outputs, higher jitter, and lacks holdover/DCO - making it unsuitable for carrier-grade SyncE or OTN timing systems requiring robust failover and fine frequency control.

Availability

SI5345A-B06103-GMR is available at Aetrix Electronics and suitable for OTN transponders, Synchronous Ethernet switches, and broadcast video infrastructure requiring stable component supply, long-term lifecycle assurance, and guaranteed G.8262 compliance.

Supply support for SI5345A-B06103-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications, industrial, and automotive markets.

The SI5345A-B06103-GMR belongs to Skyworks' Si5345 family of jitter-attenuating clock multipliers, engineered specifically for high-reliability telecom infrastructure demanding ultra-low jitter, multi-protocol timing flexibility, and seamless holdover operation.

FAQ

What is the primary function of the SI5345A-B06103-GMR in a telecom timing system?

The SI5345A-B06103-GMR serves as a jitter-attenuating clock multiplier that cleans and regenerates timing signals from noisy or unstable sources - such as recovered line clocks - while generating multiple synchronized, low-jitter outputs. In telecom systems, it enables compliance with ITU-T G.8262 for Synchronous Ethernet and supports holdover operation during input failure, ensuring uninterrupted timing integrity in OTN and carrier Ethernet platforms. SI5345A-B06103-GMR achieves this using its integrated DSPLL and programmable MultiSynth architecture.

Does the SI5345A-B06103-GMR support both I²C and SPI interfaces for configuration?

Yes, the SI5345A-B06103-GMR supports both I²C and SPI serial interfaces for device configuration, status monitoring, and non-volatile memory (NVM) programming. The interface is selected via hardware pin strapping or register setting. I²C (SCL/SDA) is commonly used for simpler two-wire integration, while SPI offers faster programming throughput. All configuration data, including frequency plans and operational modes, can be stored in on-chip OTP NVM so SI5345A-B06103-GMR powers up with a known, validated state without external host intervention.

How does the holdover functionality of the SI5345A-B06103-GMR meet ITU-T G.8262 requirements?

The SI5345A-B06103-GMR implements programmable holdover using up to 120 seconds of stored frequency history to compute an averaged holdover frequency upon input loss - minimizing phase transients and drift. Its holdover stability is optimized for G.8262 EEC Option 2 (±4.6 ppm over 24 hours) when paired with a high-stability crystal (e.g., 50 MHz TCXO on XA/XB). The device's ability to ramp exit from holdover and synchronize to gapped clocks further ensures continuous, compliant timing in carrier networks. SI5345A-B06103-GMR's documented holdover performance is verified per G.8262 Annex A test procedures.

Can the SI5345A-B06103-GMR generate different output formats simultaneously?

Yes, the SI5345A-B06103-GMR supports simultaneous output formatting across its 10 channels, including LVDS, LVPECL, LVCMOS, CML, and HCSL - each independently configurable for signal amplitude, common-mode voltage (for differential), and slew rate. This allows direct interfacing with diverse downstream devices such as FPGAs (LVDS), SERDES (CML), microcontrollers (LVCMOS), and optical modules (LVPECL) on the same board. Output drivers also feature independent supply pins (1.8 V/2.5 V/3.3 V), enabling mixed-voltage timing distribution without level shifters. SI5345A-B06103-GMR's crosspoint switch architecture enables full routing flexibility between synthesized frequencies and output drivers.

Is the SI5345A-B06103-GMR pin-compatible with other Si5345 variants like the Si5345A-D-GM1?

Yes, the SI5345A-B06103-GMR is pin-compatible with all Si5345 variants in the 64-QFN 9×9 mm package, including Si5345A-D-GM1 and Si5345B-D-GM1. They share identical pinout, footprint, and electrical interface specifications. Differences lie solely in factory-programmed NVM content and frequency synthesis capability (e.g., integer-only vs. fractional support), not mechanical or signal-level compatibility. Therefore, SI5345A-B06103-GMR can be substituted on existing PCBs designed for other Si5345A-grade 64-QFN parts without layout changes - provided the target application aligns with its configured frequency plan and feature set.

SI5345A-B06103-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5345A-B06103-GMR FAQ

1.How can I place an order for SI5345A-B06103-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5345A-B06103-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5345A-B06103-GMR reliable?

The price and inventory of SI5345A-B06103-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5345A-B06103-GMR is usually 5 days.

3.What payment methods are accepted for SI5345A-B06103-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5345A-B06103-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5345A-B06103-GMR?

SI5345A-B06103-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5345A-B06103-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5345A-B06103-GMR?

For technical support, including SI5345A-B06103-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5345A-B06103-GMR requirements.

6.How does Aetrix verify that SI5345A-B06103-GMR is sourced from the original manufacturer or authorized distributors?

All SI5345A-B06103-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5345A-B06103-GMR meets industry standards.

7.What is the process for return or replacement of SI5345A-B06103-GMR?

All SI5345A-B06103-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5345A-B06103-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5345A-B06103-GMR part is unused and in its original packaging.

Return procedure for SI5345A-B06103-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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