Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5345A-B06106-GMR

Name: SI5345A-B06106-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5345A-B06106-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5345A-B06106-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5345A-B06106-GMR.pdf

Description:: IC CLK MULTIPLIER ATTENUATOR

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,889

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5345A-B06106-GMR from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier featuring fourth-generation DSPLL™ and MultiSynth™ technologies. It delivers ultra-low 90 fs rms jitter, supports 4 differential or LVCMOS inputs and 10 programmable outputs (LVDS/LVPECL/LVCMOS/CML/HCSL), and operates across –40 to +85 °C for SyncE-compliant networking line cards.

For engineers reviewing the SI5345A-B06106-GMR datasheet, SI5345A-B06106-GMR pinout, SI5345A-B06106-GMR application, or SI5345A-B06106-GMR equivalent, this device enables hitless input switching, digitally programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), G.8262 EEC Option 1/2 compliance, and in-circuit NVM configuration via I²C/SPI - critical for OTN transponders and carrier Ethernet switches requiring deterministic phase alignment and holdover stability.

Technical Context

The SI5345A-B06106-GMR implements a fourth-generation DSPLL architecture with fully integrated loop filter and fractional-N frequency synthesis, enabling precise jitter attenuation and any-output-frequency generation from any input frequency. Its MultiSynth output dividers support both integer and fractional division, while the crosspoint switch routes any synthesized frequency to any of the 10 outputs.

It operates in free-run, locked, holdover, and zero-delay modes, with programmable holdover averaging over up to 120 s of historical frequency data and ramped holdover exit using user-selectable slew rates (0.2–40,000 ppm/s). Input qualification includes LOS, OOF, and LOL monitoring, and glitchless switching supports ±500 ppm input frequency offsets.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (rms)	90 fs - meets stringent ITU-T G.8262 EEC Option 1/2 requirements for Synchronous Ethernet timing recovery.
Input range (diff)	8 kHz–750 MHz - supports OC-192/STM-64, 10G/100G Ethernet, and SONET/SDH reference clocks.
Output range (diff)	100 Hz–1028 MHz - covers all common network PHY clocking needs including 156.25 MHz, 311.04 MHz, and 622.08 MHz.
Jitter BW control	0.1 Hz–4 kHz digital programming - allows optimization for wander suppression (low BW) or fast lock (high BW) per application.
Supply voltages	VDD = 1.8 V ±5%, VDDA = 3.3 V ±5% - enables low-power operation with independent 1.8/2.5/3.3 V output supply pins.
Operating temp	–40 to +85 °C - qualified for industrial-grade telecom and broadcast video equipment deployment.
Crystal range	25–54 MHz external XTAL - internal loading capacitors eliminate external components and reduce noise coupling.

Pinout & Package

SI5345A-B06106-GMR is housed in a 64-pin QFN package (9 × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5345 Rev D datasheet Section 9 (Pin Descriptions) and Figure 10.1 (Package Diagram).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential or LVCMOS input	Accepts primary reference clocks; supports gapped clock locking and automatic/manual selection with hitless switching.
OUT0–OUT9	Configurable output driver	Programmable for LVDS/LVPECL/LVCMOS/CML/HCSL; each has independent amplitude, common-mode, and enable control.
XA/XB	Crystal oscillator interface	Connects 25–54 MHz fundamental-mode crystal; internal load caps eliminate external components and improve jitter immunity.
SCL/SDA	I²C serial interface	Two-wire bus for configuration, status readback, and NVM programming; supports hot-plug and in-system updates.
INTRb	Interrupt output	Active-low open-drain flag indicating LOS, OOF, LOL, or other fault conditions per register-mapped status bits.

Key Features

Feature	Design Value
Hitless input switching	Eliminates phase transients when switching between fractionally related inputs (e.g., 156.25 MHz ↔ 311.04 MHz), preserving system timing integrity.
Programmable holdover	Uses 120-second frequency history with configurable window/delay to minimize phase jump during input failure - essential for SyncE pizza-box resilience.
Digital DCO mode	Enables fine frequency tuning down to 0.001 ppb step size via FINC/FDEC pins or SPI, supporting IEEE 1588 PTP slave clock adjustment.
Zero-delay mode	Configures IN3 as feedback input (FB_IN) to align output phase with selected input - required for deterministic latency in packet-processing pipelines.
Status monitoring	Real-time detection of Loss-of-Signal (LOS), Out-of-Frequency (OOF), and Loss-of-Lock (LOL) with interrupt assertion and register flags.

Applications

OTN Muxponder	Carrier Ethernet Switch
Use Scenario: Aggregating multiple client-side 10G/100G signals into a single OTU4 line-side interface with strict jitter accumulation limits. IC Role / Device Role / Timing Role: Jitter attenuator and multi-rate clock multiplier generating synchronized 156.25 MHz, 311.04 MHz, and 622.08 MHz clocks from diverse input references. Use Value: 90 fs rms jitter ensures OTU4 transmit jitter remains within ITU-T G.709 mask; programmable holdover maintains timing continuity during upstream link failure.	Use Scenario: Providing phase-aligned, low-wander clocks to multiple line cards and fabric interfaces in a modular chassis-based switch. IC Role / Device Role / Timing Role: Centralized timing hub distributing G.8262-compliant SyncE clocks across backplane and pluggable modules. Use Value: Meets EEC Option 1/2 requirements with <0.1 ppm wander; automatic input switching ensures seamless failover between primary and backup grandmaster clocks.
Broadcast Video Router	Test & Measurement Instrument
Use Scenario: Synchronizing SDI/HD-SDI/3G-SDI signal paths in a frame-accurate video routing matrix with genlock and tri-level sync sources. IC Role / Device Role / Timing Role: Multi-format clock generator producing 27 MHz, 74.25 MHz, and 148.5 MHz outputs from SMPTE ST 2059-2 PTP or analog black burst inputs. Use Value: Ultra-low jitter preserves eye diagram integrity across cascaded distribution; LVCMOS/LVDS output flexibility matches diverse receiver IC requirements.	Use Scenario: Serving as a reconfigurable jitter test source or clean reference in high-speed oscilloscopes, BERTs, and signal analyzers. IC Role / Device Role / Timing Role: Programmable jitter attenuator and frequency synthesizer generating calibrated clock stimuli with controlled phase noise profiles. Use Value: Digitally adjustable jitter attenuation bandwidth (0.1 Hz–4 kHz) enables precise emulation of network impairments; DCO mode supports dynamic frequency sweeps for PLL characterization.

OTN Muxponder

Carrier Ethernet Switch

Use Scenario: Aggregating multiple client-side 10G/100G signals into a single OTU4 line-side interface with strict jitter accumulation limits.

IC Role / Device Role / Timing Role: Jitter attenuator and multi-rate clock multiplier generating synchronized 156.25 MHz, 311.04 MHz, and 622.08 MHz clocks from diverse input references.

Use Value: 90 fs rms jitter ensures OTU4 transmit jitter remains within ITU-T G.709 mask; programmable holdover maintains timing continuity during upstream link failure.

Use Scenario: Providing phase-aligned, low-wander clocks to multiple line cards and fabric interfaces in a modular chassis-based switch.

IC Role / Device Role / Timing Role: Centralized timing hub distributing G.8262-compliant SyncE clocks across backplane and pluggable modules.

Use Value: Meets EEC Option 1/2 requirements with <0.1 ppm wander; automatic input switching ensures seamless failover between primary and backup grandmaster clocks.

Broadcast Video Router

Test & Measurement Instrument

Use Scenario: Synchronizing SDI/HD-SDI/3G-SDI signal paths in a frame-accurate video routing matrix with genlock and tri-level sync sources.

IC Role / Device Role / Timing Role: Multi-format clock generator producing 27 MHz, 74.25 MHz, and 148.5 MHz outputs from SMPTE ST 2059-2 PTP or analog black burst inputs.

Use Value: Ultra-low jitter preserves eye diagram integrity across cascaded distribution; LVCMOS/LVDS output flexibility matches diverse receiver IC requirements.

Use Scenario: Serving as a reconfigurable jitter test source or clean reference in high-speed oscilloscopes, BERTs, and signal analyzers.

IC Role / Device Role / Timing Role: Programmable jitter attenuator and frequency synthesizer generating calibrated clock stimuli with controlled phase noise profiles.

Use Value: Digitally adjustable jitter attenuation bandwidth (0.1 Hz–4 kHz) enables precise emulation of network impairments; DCO mode supports dynamic frequency sweeps for PLL characterization.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5345B-D-GM1	Same 64-QFN package and pinout; limited to 350 MHz max output frequency (vs. 1028 MHz).	Suitable for sub-10G applications only (e.g., 1G/2.5G Ethernet, CPRI); not viable for 100G line cards or OTU4.	Select when output frequencies ≤350 MHz simplify design and reduce cost; verify clock tree coverage before substitution.
LMK04832ISQE/NOPB	TI dual-loop jitter cleaner; 3.1 GHz max input, 3.1 GHz max output; requires external loop filter components.	Higher max frequency but larger solution size; lacks integrated crystal interface and zero-delay mode.	Prefer for RF/data converter timing where >1 GHz outputs or ultra-wideband jitter cleaning is needed; avoid if board space or crystal integration is constrained.

Compared with SI5345A-B06106-GMR, Si5345B-D-GM1 trades maximum output frequency for cost reduction in lower-speed systems, while LMK04832ISQE/NOPB offers higher bandwidth at the expense of external component count and missing SyncE-specific features like programmable holdover history.

Availability

SI5345A-B06106-GMR is available at Aetrix Electronics and suitable for OTN muxponders, carrier Ethernet switches, and broadcast video infrastructure requiring stable component supply, long-term lifecycle assurance, and G.8262-compliant timing performance.

Supply support for SI5345A-B06106-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications, automotive, and industrial markets.

The Si5345 family is designed specifically for high-performance timing in telecom infrastructure, delivering jitter-attenuated, multi-output clock synthesis with SyncE and ITU-T compliance for next-generation networking hardware.

FAQ

What is the primary function of the SI5345A-B06106-GMR in a telecom timing architecture?

The SI5345A-B06106-GMR serves as a jitter-attenuating clock multiplier that cleans and regenerates timing signals from noisy or unstable references. In telecom systems, it generates multiple low-jitter output clocks (up to 1028 MHz) from up to four input sources while meeting ITU-T G.8262 EEC Option 1/2 requirements - ensuring synchronization integrity across OTN, SyncE, and packet-optical platforms. Its holdover capability maintains timing continuity during input failures.

Does the SI5345A-B06106-GMR support automatic input clock switching with hitless transition?

Yes, the SI5345A-B06106-GMR supports both automatic and manual input clock switching with hitless capability. Hitless switching occurs when transitioning between inputs with fixed phase relationships (e.g., integer or fractional frequency ratios), preventing phase discontinuities at the outputs. The device uses its DSPLL architecture to absorb phase differences during the switch - a key feature confirmed in the Si5345 Rev D datasheet Section 3.7.3 and validated for use in carrier-grade Ethernet switches.

What crystal frequency range is supported by the SI5345A-B06106-GMR, and why is 48–54 MHz recommended?

The SI5345A-B06106-GMR supports external crystals from 25 to 54 MHz. A 48–54 MHz crystal is recommended because it delivers optimal jitter performance due to improved phase noise characteristics and better utilization of the internal oscillator circuitry. This range also aligns with common TCXO offerings used in SyncE pizza-box applications where holdover stability is critical. The device integrates internal loading capacitors, eliminating external components and reducing noise coupling.

Can the SI5345A-B06106-GMR generate different output formats on individual pins, such as LVDS on OUT0 and LVCMOS on OUT1?

Yes, the SI5345A-B06106-GMR supports independent configuration of each of its 10 outputs for LVDS, LVPECL, LVCMOS, CML, or HCSL signaling. Each output includes programmable amplitude, common-mode voltage (for differential), and drive strength settings. This flexibility allows mixed-signal clock distribution - for example, LVDS to FPGA transceivers and LVCMOS to microcontrollers - without external level-shifting components, as documented in Section 3.9.2 of the Si5345 Rev D datasheet.

How does the holdover functionality of the SI5345A-B06106-GMR improve system reliability in SyncE applications?

The SI5345A-B06106-GMR's holdover functionality improves SyncE reliability by maintaining accurate timing during input reference loss. It stores up to 120 seconds of historical frequency data while locked, then calculates an averaged holdover frequency from a programmable window within that history. This minimizes phase disturbance upon entry/exit and ensures wander remains within ITU-T G.8262 limits - a requirement verified for EEC Option 1/2 compliance and essential for metro and access network resilience.

SI5345A-B06106-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5345A-B06106-GMR FAQ

1.How can I place an order for SI5345A-B06106-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5345A-B06106-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5345A-B06106-GMR reliable?

The price and inventory of SI5345A-B06106-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5345A-B06106-GMR is usually 5 days.

3.What payment methods are accepted for SI5345A-B06106-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5345A-B06106-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5345A-B06106-GMR?

SI5345A-B06106-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5345A-B06106-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5345A-B06106-GMR?

For technical support, including SI5345A-B06106-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5345A-B06106-GMR requirements.

6.How does Aetrix verify that SI5345A-B06106-GMR is sourced from the original manufacturer or authorized distributors?

All SI5345A-B06106-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5345A-B06106-GMR meets industry standards.

7.What is the process for return or replacement of SI5345A-B06106-GMR?

All SI5345A-B06106-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5345A-B06106-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5345A-B06106-GMR part is unused and in its original packaging.

Return procedure for SI5345A-B06106-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…