Skyworks Solutions Inc. SI5345A-B06746-GM

Overview

SI5345A-B06746-GM from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier featuring fourth-generation DSPLL™ and MultiSynth™ architectures. It delivers ultra-low 90 fs rms jitter, supports differential inputs up to 750 MHz and outputs up to 1028 MHz, and operates in free-run, locked, or holdover modes - enabling precise clock synthesis for SyncE-compliant 100 GbE line cards.

For engineers reviewing the SI5345A-B06746-GM datasheet, SI5345A-B06746-GM pinout, SI5345A-B06746-GM application, or SI5345A-B06746-GM equivalent, key selection considerations include its programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), G.8262 EEC Option 1/2 compliance, 64-QFN 9×9 mm package, I²C/SPI configurability, and factory preprogrammed NVM configuration.

Technical Context

The SI5345A-B06746-GM implements a digitally controlled DSPLL with fully integrated loop filter and programmable loop bandwidth (0.1 Hz–4 kHz), enabling application-tuned jitter filtering. Its MultiSynth architecture uses fractional-N synthesis across ten independent output paths, each configurable for LVDS, LVPECL, LVCMOS, CML, or HCSL signaling with programmable amplitude and common-mode voltage.

It supports hitless, glitchless, and ramped input switching between four differential or LVCMOS inputs (IN0–IN3), with automatic fault monitoring (LOS/OOF/LOL) and status flag reporting via INTRb. The device integrates an on-chip oscillator for crystal reference (25–54 MHz) and operates across –40°C to +85°C with dual supply rails (VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%).

Key Specifications

Pinout & Package

The SI5345A-B06746-GM is housed in a 64-pin QFN package (9×9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5345 Rev D datasheet Section 9 (Pin Descriptions) and Figure 10.1 (package diagram). All pins support 1.8/2.5/3.3 V IO compatibility depending on configuration.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator/clock multiplier applications.

Compared with SI5345B-D-GM, the SI5345A-B06746-GM supports full 1028 MHz output and fractional synthesis - essential for 100 GbE and OTN. Versus LMK04832, it offers integrated crystal oscillator, factory NVM, and gapped-clock resilience - reducing BOM count and improving system robustness in telecom infrastructure.

Availability

SI5345A-B06746-GM is available at Aetrix Electronics and suitable for 100 GbE line cards, OTN muxponders, and Synchronous Ethernet switches requiring stable component supply, long-term lifecycle assurance, and factory-preprogrammed timing configurations.

Supply support for SI5345A-B06746-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5345 family is designed specifically for high-performance timing in carrier-grade networking and communications infrastructure - delivering ultra-low jitter, multi-frequency synthesis, and robust holdover for SyncE, OTN, and broadcast video systems.

FAQ

What is the primary function of the SI5345A-B06746-GM in a telecom timing system?

The SI5345A-B06746-GM serves as a jitter-attenuating clock multiplier that cleans noisy input references and synthesizes multiple precise output frequencies. In telecom systems, it enables ITU-T G.8262 Synchronous Ethernet compliance by providing ultra-low 90 fs rms jitter outputs while maintaining lock during reference disturbances - a core requirement for SI5345A-B06746-GM deployment in 100 GbE line cards and OTN equipment.

Does the SI5345A-B06746-GM require external loop filter components?

No, the SI5345A-B06746-GM integrates the entire DSPLL loop filter on-chip, eliminating discrete capacitors and resistors. This design prevents noise coupling from PCB traces and improves jitter performance consistency across units - a key differentiator of the SI5345A-B06746-GM versus traditional PLL ICs requiring external passive components.

How does the SI5345A-B06746-GM handle loss of input reference?

Upon input reference failure, the SI5345A-B06746-GM automatically enters holdover mode using a programmable 120-second frequency history buffer. It calculates the final holdover frequency from a user-defined window within that history, minimizing phase disturbance - a critical behavior confirmed in SI5345A-B06746-GM's G.8262 EEC Option 2 qualification for carrier networks.

Can the SI5345A-B06746-GM generate both LVDS and LVCMOS outputs simultaneously?

Yes, the SI5345A-B06746-GM supports independent configuration of each of its ten outputs for LVDS, LVPECL, CML, HCSL, or LVCMOS signaling, with programmable amplitude and common-mode voltage. This flexibility allows SI5345A-B06746-GM to drive mixed-technology interfaces - such as SerDes receivers (LVDS) and FPGA logic (LVCMOS) - from a single device.

Is the SI5345A-B06746-GM preprogrammed at the factory?

Yes, the "B06746" suffix in SI5345A-B06746-GM indicates a factory preprogrammed configuration stored in on-chip non-volatile memory (NVM). This means SI5345A-B06746-GM powers up immediately with validated output frequencies, loop bandwidth, and input selection settings - eliminating post-power-up I²C/SPI initialization in time-critical carrier systems.