Skyworks Solutions Inc. SI5345A-C-GM

Overview

SI5345A-C-GM from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier with fourth-generation DSPLL™ and MultiSynth™ architecture. It delivers 90 fs rms jitter, supports 4 differential or LVCMOS inputs and 10 programmable outputs (LVDS/LVPECL/LVCMOS/CML/HCSL), and operates across –40 to +85 °C for SyncE-compliant telecom timing in OTN transponders and 100 GbE line cards.

For engineers reviewing the SI5345A-C-GM datasheet, SI5345A-C-GM pinout, SI5345A-C-GM application, or SI5345A-C-GM equivalent, key selection criteria include jitter attenuation bandwidth (0.1 Hz–4 kHz), G.8262 EEC Option 1/2 compliance, hitless/ramped input switching, DCO mode (0.001 ppb step), and factory-programmable NVM configuration via I²C/SPI.

Technical Context

The SI5345A-C-GM implements a digitally controlled DSPLL with fully integrated loop filter and programmable loop bandwidth (0.1 Hz–4 kHz), enabling precise jitter filtering without external components. Its MultiSynth architecture uses fractional-N synthesis (Mn/Md) and integer-R division to generate any output frequency from any input frequency across 100 Hz–1028 MHz (differential) or 100 Hz–250 MHz (LVCMOS).

It supports three operational modes-freerun (crystal-referenced), locked (input-synchronized), and holdover (averaged historical frequency)-with automatic/manual input switching, status monitoring (LOS/OOF/LOL), and glitchless on-the-fly output reconfiguration. Core supply is 1.8 V ±5%, analog supply 3.3 V ±5%, with independent 1.8/2.5/3.3 V output supply pins.

Key Specifications

Pinout & Package

The SI5345A-C-GM is housed in a 64-pin QFN package (9 × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5345 Rev D datasheet Section 9 (Pin Descriptions).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Compared with SI5345A-C-GM, Si5345B-C-GM sacrifices frequency range and fractional synthesis for lower cost, while LMK5B33414 trades integrated crystal support and simpler layout for JESD204B-specific features and higher output count - making SI5345A-C-GM optimal for crystal-based, wideband telecom timing where jitter, holdover, and ease of configuration are primary.

Availability

SI5345A-C-GM is available at Aetrix Electronics and suitable for OTN transponders, Carrier Ethernet switches, and broadcast video equipment requiring stable component supply, long-term lifecycle assurance, and G.8262-compliant timing performance.

Supply support for SI5345A-C-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5345 family is designed specifically for high-performance timing in telecom infrastructure, delivering ultra-low jitter, flexible clock synthesis, and robust holdover for SyncE, OTN, and packet-optical systems.

FAQ

What is the maximum differential output frequency supported by the SI5345A-C-GM?

The SI5345A-C-GM supports differential output frequencies up to 1028 MHz, enabling direct clocking of 100G/400G SerDes lanes and high-speed ADC/DAC interfaces. This specification is confirmed in the Si5345/44/42 Rev D datasheet Section 1. Features List and Table 2. Ordering Guide. The SI5345A-C-GM variant retains full 1028 MHz capability, unlike the B-variant which is limited to 350 MHz.

Does the SI5345A-C-GM include an integrated crystal oscillator circuit?

Yes, the SI5345A-C-GM integrates a crystal oscillator (OSC) with internal loading capacitors for 25–54 MHz fundamental-mode crystals on XA/XB pins. This eliminates external capacitors and reduces noise coupling, directly contributing to its 90 fs rms jitter performance. The oscillator serves as the reference for freerun and holdover modes, as detailed in Section 3.5 of the Rev D datasheet.

How does the SI5345A-C-GM achieve hitless input switching?

The SI5345A-C-GM achieves hitless input switching by absorbing phase differences between two input clocks that are frequency-locked or fractionally related (e.g., 155.52 MHz and 622.08 MHz). When enabled, the DSPLL adjusts its internal phase alignment during the switch rather than propagating transient phase offsets to outputs - a feature verified in Section 3.7.3 of the Rev D datasheet and critical for maintaining deterministic latency in OTN systems.

What supply voltages are required for the SI5345A-C-GM core and outputs?

The SI5345A-C-GM requires VDD = 1.8 V ±5% for digital core logic and VDDA = 3.3 V ±5% for analog circuits including the DSPLL and oscillator. Each of its 10 outputs has independent supply pins supporting 1.8 V, 2.5 V, or 3.3 V - enabling mixed-voltage board designs without level shifters. These values are specified in Section 1. Features List and Electrical Specifications Table 5.1 of the Rev D datasheet.

Is the SI5345A-C-GM compliant with ITU-T G.8262 Synchronous Ethernet standards?

Yes, the SI5345A-C-GM meets ITU-T G.8262 EEC Option 1 and Option 2 requirements for Enhanced Equipment Clocks. Its 90 fs rms jitter, programmable jitter attenuation bandwidth (0.1 Hz–4 kHz), and holdover stability with historical averaging ensure compliance in both locked and holdover modes - explicitly stated in the "KEY FEATURES" section and validated in Typical Operating Characteristics (Section 8) of the Rev D datasheet.