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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5345B-B03544-GMR

Name: SI5345B-B03544-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5345B-B03544-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5345B-B03544-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5345B-B03544-GMR.pdf

Description:: IC CLK MULTIPLIER ATTENUATOR

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Product details

Overview

SI5345B-B03544-GMR from Skyworks is a 10-channel, any-frequency jitter attenuator/clock multiplier with fourth-generation DSPLL™ and MultiSynth™ architecture. It delivers ultra-low 90 fs rms jitter, supports differential inputs up to 750 MHz and outputs up to 1028 MHz, and operates in free-run, locked, or holdover modes - enabling precise clock synthesis for SyncE-compliant 100 GbE line cards.

For engineers reviewing the SI5345B-B03544-GMR datasheet, SI5345B-B03544-GMR pinout, SI5345B-B03544-GMR application, or SI5345B-B03544-GMR equivalent, key selection considerations include its 0.1–4 kHz digitally programmable jitter attenuation bandwidth, G.8262 EEC Option 1/2 compliance, I²C/SPI configurability with on-chip NVM, and support for LVDS/LVPECL/LVCMOS/CML/HCSL output formats.

Technical Context

The SI5345B-B03544-GMR implements a fourth-generation DSPLL with integrated loop filter and digitally programmable loop bandwidth (0.1 Hz–4 kHz), enabling application-level jitter optimization. Its MultiSynth™ fractional-N synthesis allows independent integer/fractional division per output channel, supporting glitchless on-the-fly frequency changes and DCO mode with 0.001 ppb step size.

It features four configurable inputs (differential or LVCMOS), automatic/manual hitless input switching, status monitoring (LOS/OOF/LOL), and programmable holdover using up to 120 s of historical frequency data - all controlled via I²C or SPI with factory-programmable OTP memory.

Key Specifications

Parameter	Value and Actual Design Meaning
Jitter (rms)	90 fs - meets stringent SyncE EEC Option 1/2 requirements for 100 GbE transport
Input range (diff)	8 kHz–750 MHz - supports OC-192, SONET, and high-speed SerDes reference clocks
Output range (diff)	100 Hz–1028 MHz - covers Ethernet, PCIe, and CPRI frequencies without external dividers
Jitter BW control	0.1 Hz–4 kHz - digitally selectable to optimize attenuation vs. wander trade-off
Supply voltages	VDD = 1.8 V ±5%; VDDA = 3.3 V ±5% - enables low-power core with noise-isolated analog rail
Operating temp	–40 °C to +85 °C - qualified for industrial and telecom infrastructure environments
Package	64-QFN, 9×9 mm - surface-mount compatible with standard PCB assembly processes

Pinout & Package

The SI5345B-B03544-GMR is housed in a 64-pin QFN package (9×9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per Skyworks Si5345 Rev D datasheet Section 9 (Pin Descriptions).

Pin/Terminal	Circuit Role	Design Meaning
IN0–IN3	Differential/LVCMOS clock inputs	Four independent inputs with LOS detection; IN3 serves as FB_IN in zero-delay mode
OUT0–OUT9	Programmable clock outputs	10 outputs supporting LVDS/LVPECL/LVCMOS/CML/HCSL with independent amplitude/format control
XA/XB	Crytal oscillator terminals	Connects 25–54 MHz fundamental-mode crystal; internal load caps eliminate external components
SCL/SDA	I²C serial interface	Two-wire bus for configuration and status readback; supports hot-plug initialization
INTRb	Interrupt output	Active-low open-drain flag indicating LOS/OOF/LOL events for system fault management
RSTb	Hardware reset	Asynchronous active-low pin triggering full hard reset with NVM reload

Key Features

Feature	Design Value
Any-frequency synthesis	Generates arbitrary output frequencies from any input via fractional-N MultiSynth™ with P/N/R dividers
Hitless input switching	Eliminates phase transients when switching between fractionally related inputs (e.g., 156.25 MHz ↔ 312.5 MHz)
Programmable holdover	Uses 120 s of stored frequency history with user-defined averaging window to minimize phase jump on input failure
Fastlock acquisition	Temporarily raises loop bandwidth (100 Hz–4 kHz) during lock acquisition to reduce settling time by >10×
DCO mode	Enables fine frequency tuning (0.001 ppb steps) for timing calibration or packet delay compensation

Applications

OTN Muxponders	100 GbE Synchronous Ethernet
Use Scenario: Aggregating multiple client-side OTN signals into a single line-side wavelength with strict jitter limits. IC Role / Device Role / Timing Role: Jitter attenuator and multi-rate clock multiplier generating clean 156.25 MHz, 311.04 MHz, and 622.08 MHz clocks from recovered line references. Use Value: Meets ITU-T G.8262 EEC Option 2 mask for ≤90 fs rms jitter, ensuring BER <1e−12 across DWDM links.	Use Scenario: Providing traceable, phase-aligned clocks across distributed 100 GbE switch fabric with redundant timing sources. IC Role / Device Role / Timing Role: Primary clock synthesizer with automatic input failover and holdover, synchronized to primary and backup SyncE inputs. Use Value: Maintains sub-50 ns phase continuity during input switching and ≤0.1 ppm frequency stability in holdover using 48–54 MHz crystal reference.
Broadcast Video Timing	Test & Measurement Equipment
Use Scenario: Generating genlock-capable pixel clocks (e.g., 74.25 MHz, 148.5 MHz) and audio sample clocks (48 kHz, 96 kHz) from a common reference. IC Role / Device Role / Timing Role: Multi-output jitter cleaner delivering deterministic phase relationships between video and audio domains. Use Value: Achieves <1 ps peak-to-peak jitter on LVDS outputs, preserving SMPTE ST 2082-1 timing integrity for 4K/8K UHD signal distribution.	Use Scenario: Serving as programmable clock source in high-resolution oscilloscopes and bit-error-rate testers requiring ultra-low-jitter sampling clocks. IC Role / Device Role / Timing Role: Reference clock generator with DCO fine-tuning and fastlock for rapid test setup reconfiguration. Use Value: Enables <0.01 ppm frequency resolution and <100 µs lock time to new frequencies, accelerating automated test sequences.

OTN Muxponders

100 GbE Synchronous Ethernet

Use Scenario: Aggregating multiple client-side OTN signals into a single line-side wavelength with strict jitter limits.

IC Role / Device Role / Timing Role: Jitter attenuator and multi-rate clock multiplier generating clean 156.25 MHz, 311.04 MHz, and 622.08 MHz clocks from recovered line references.

Use Value: Meets ITU-T G.8262 EEC Option 2 mask for ≤90 fs rms jitter, ensuring BER <1e−12 across DWDM links.

Use Scenario: Providing traceable, phase-aligned clocks across distributed 100 GbE switch fabric with redundant timing sources.

IC Role / Device Role / Timing Role: Primary clock synthesizer with automatic input failover and holdover, synchronized to primary and backup SyncE inputs.

Use Value: Maintains sub-50 ns phase continuity during input switching and ≤0.1 ppm frequency stability in holdover using 48–54 MHz crystal reference.

Broadcast Video Timing

Test & Measurement Equipment

Use Scenario: Generating genlock-capable pixel clocks (e.g., 74.25 MHz, 148.5 MHz) and audio sample clocks (48 kHz, 96 kHz) from a common reference.

IC Role / Device Role / Timing Role: Multi-output jitter cleaner delivering deterministic phase relationships between video and audio domains.

Use Value: Achieves <1 ps peak-to-peak jitter on LVDS outputs, preserving SMPTE ST 2082-1 timing integrity for 4K/8K UHD signal distribution.

Use Scenario: Serving as programmable clock source in high-resolution oscilloscopes and bit-error-rate testers requiring ultra-low-jitter sampling clocks.

IC Role / Device Role / Timing Role: Reference clock generator with DCO fine-tuning and fastlock for rapid test setup reconfiguration.

Use Value: Enables <0.01 ppm frequency resolution and <100 µs lock time to new frequencies, accelerating automated test sequences.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter attenuator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5345A-B03544-GMR	Supports full 0.001–1028 MHz output range with integer+fractional synthesis; SI5345B-B03544-GMR limited to ≤350 MHz	Required for >350 MHz outputs (e.g., 622.08 MHz SONET, 1.2288 GHz CPRI); not needed for 10/40/100 GbE base rates	Select SI5345A-B03544-GMR only if outputs above 350 MHz are required; SI5345B-B03544-GMR reduces cost and simplifies validation for sub-350 MHz use cases
LMK04832RHAR	Triple PLL architecture with separate jitter cleaning and clock distribution stages; higher power (1.2 W vs. 0.65 W), no on-chip NVM	Better suited for systems requiring cascaded jitter cleaning + fanout (e.g., radar beamforming), less optimal for single-chip any-frequency synthesis	Choose LMK04832RHAR when hierarchical timing distribution is needed; SI5345B-B03544-GMR offers simpler integration and lower BOM count for direct jitter attenuation/multiplication

Compared with Si5345A-B03544-GMR, the SI5345B-B03544-GMR trades maximum output frequency for cost and design simplicity in sub-350 MHz applications; compared with LMK04832RHAR, it provides monolithic synthesis with embedded NVM at lower power, but lacks multi-stage PLL flexibility for complex timing trees.

Availability

SI5345B-B03544-GMR is available at Aetrix Electronics and suitable for 100 GbE line cards, OTN muxponders, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5345B-B03544-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications, automotive, and industrial markets.

The Si5345 family is designed for high-performance timing in telecom infrastructure and data center networking, where ultra-low jitter, multi-channel flexibility, and robust holdover operation are critical.

FAQ

What is the maximum output frequency supported by the SI5345B-B03544-GMR?

The SI5345B-B03544-GMR supports differential output frequencies up to 350 MHz, as specified in the Skyworks Ordering Guide for "B" variant devices. This is lower than the full 1028 MHz capability of the "A" variant (e.g., SI5345A-B03544-GMR), making it optimized for 10/40/100 GbE, OTN, and broadcast video applications where higher frequencies are unnecessary. The SI5345B-B03544-GMR maintains identical jitter performance (90 fs rms) and feature set within its rated range.

Does the SI5345B-B03544-GMR require an external crystal, and what frequency range is supported?

Yes, the SI5345B-B03544-GMR requires an external crystal connected to XA/XB pins, supporting 25–54 MHz fundamental-mode crystals. Skyworks recommends 48–54 MHz for optimal jitter performance. The device integrates internal load capacitors, eliminating external capacitors and reducing noise coupling. For SyncE pizza-box applications with 0.1 Hz loop bandwidth, a TCXO is recommended instead of a crystal to minimize wander during holdover.

How does the SI5345B-B03544-GMR handle input clock failures, and what holdover accuracy can be expected?

The SI5345B-B03544-GMR automatically enters holdover mode upon input failure, using up to 120 seconds of stored frequency history to compute an averaged holdover frequency. Accuracy depends on the external crystal: with a ±10 ppm crystal, holdover drift is ±10 ppm; with a ±0.1 ppm TCXO, drift is ±0.1 ppm. The holdover window size and delay are programmable to exclude corrupted pre-failure data, minimizing phase disturbance during transition.

Can the SI5345B-B03544-GMR generate different output formats simultaneously, and which ones are supported?

Yes, the SI5345B-B03544-GMR supports simultaneous mixed-format outputs across its 10 channels. Each output is independently configurable for LVDS, LVPECL, LVCMOS, CML, or HCSL, with programmable amplitude, common-mode voltage (for differential), and slew rate. This enables direct interfacing with diverse PHYs (e.g., Ethernet MACs, SerDes, FPGAs) without level-shifting components - a key advantage over single-format clock generators.

Is factory programming available for the SI5345B-B03544-GMR, and how is it configured?

Yes, Skyworks offers factory preprogramming of the SI5345B-B03544-GMR using ClockBuilder Pro™ software. Configuration data is stored in on-chip one-time-programmable (OTP) NVM, enabling known-frequency power-up without host processor intervention. Custom part numbers (e.g., Si5345B-Dxxxxx-GM) are assigned by Skyworks; Aetrix Electronics supports ordering both blank and preprogrammed units with full configuration documentation and validation reports for the SI5345B-B03544-GMR.

SI5345B-B03544-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5345B-B03544-GMR FAQ

1.How can I place an order for SI5345B-B03544-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5345B-B03544-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5345B-B03544-GMR reliable?

The price and inventory of SI5345B-B03544-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5345B-B03544-GMR is usually 5 days.

3.What payment methods are accepted for SI5345B-B03544-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5345B-B03544-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5345B-B03544-GMR?

SI5345B-B03544-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5345B-B03544-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5345B-B03544-GMR?

For technical support, including SI5345B-B03544-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5345B-B03544-GMR requirements.

6.How does Aetrix verify that SI5345B-B03544-GMR is sourced from the original manufacturer or authorized distributors?

All SI5345B-B03544-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5345B-B03544-GMR meets industry standards.

7.What is the process for return or replacement of SI5345B-B03544-GMR?

All SI5345B-B03544-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5345B-B03544-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5345B-B03544-GMR part is unused and in its original packaging.

Return procedure for SI5345B-B03544-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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